|
|
PDF LTC4318 Data sheet ( Hoja de datos )
| Número de pieza | LTC4318 | |
| Descripción | Dual I2C/SMBus Address Translator | |
| Fabricantes | Linear | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LTC4318 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
LTC4318
Dual I2C/SMBus
Address Translator
Features
nn Allows Multiple Slaves with the Same Address to
Coexist on the Same Bus
nn Resistor Configurable Address Translation
nn No Software Programming Required
nn Compatible with SMBus, I2C and I2C Fast Mode
nn Pass-Through Mode Allows General Call Addressing
nn ±4kV HBM ESD Ruggedness
nn Level Translation for 2.5V, 3.3V and 5V Buses
nn Stuck Bus Timeout
nn Prevents SDA and SCL Corruption During Live Board
Insertion and Removal
nn Support Bus Hot Swap™
nn 20-Lead QFN 4mm × 4mm Package
Applications
nn I2C, SMBus Address Expansion
nn Address Translation
nn Servers
nn Telecom
Description
The LTC®4318 enables the hardwired address of one or
more I2C or SMBus slave devices to be translated to a
different address. This allows slaves with the same hard-
wired address to coexist on the same bus. Only discrete
resistors are needed to select the new address and no
software programming is required. Up to 127 different
address translations are available.
The LTC4318 incorporates a pass-through mode which
disables the address translations and allows general call
addressing by the master. The LTC4318 is designed to
automatically recover from abnormal bus conditions like
bus stuck low or premature STOP bits.
PART NUMBER
NUMBER OF INPUT NUMBER OF OUTPUT
CHANNELS
CHANNELS
LTC4316
11
LTC4317
12
LTC4318
22
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot
Swap is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 6356140, 6650174, 7032051,
7478286. Patent pending.
Typical Application
3.3V
SCL
MASTER #1
SDA
SENDS
ADDRESS 0x34
3.3V
SCL
MASTER #1
SDA
SENDS
ADDRESS 0x32
3.3V
VCC
SCLIN1 SCLOUT1
TRANSLATES
BY 0x02
SDAIN1 SDAOUT1
LTC4318
ENABLE1 READY1
ENABLE2 READY2
TRANSLATES
SCLIN2 SCLOUT2 BY 0x04
SDAIN2 SDAOUT2
XORH2
GND XORH1
XORL2 XORL1
845k 61.9k 93.1k
4318 TA01a
5V
SCL
SLAVE# 1
SDA
RECEIVES
ADDRESS 0X36
5V
SCL
SLAVE# 2
SDA
RECEIVES
ADDRESS 0X36
START
ADDRESS BITS
R/W ACK
BIT BIT
a6 a5 a4 a3 a2 a1 a0
SCLIN1
SDAIN1
TRANSLATION
BYTE
SDAOUT1
0 0 1 1 0 1 0 0 = 0x34
0 0 0 0 0 0 1 0 = 0x02
0 0 1 1 0 1 1 0 = 0x36
4318 TA01b
For more information www.linear.com/LTC4318
4318f
1
1 page  
LTC4318
Typical Performance Characteristics TA = 25°C, VCC = 3.3V unless otherwise noted.
SDAOUT Fall Delay vs Bus
Capacitance
300
275
250 VCC = 5V
225 VCC = 3.3V
200 VCC = 2.25V
175
150
125
100
0
200 400 600 800 1000
CBUS (pF)
4318 G07
SDAOUT Fall Time vs
Temperature
120 C = 100pF
100
VIN = 5V
80
VIN = 3.3V
60
40 VIN = 2.25V
20
–50
–25 0 25 50
TEMPERATURE (°C)
75 100
4318 G08
SDAOUT Fall Time vs Bus
Capacitance
120
100 VIN = 5V
80
VIN = 3.3V
60
40 VIN = 2.25V
20
0
200 400 600 800 1000
CBUS (pF)
4318 G09
Pin Functions
XORL1/XORL2: Translator XOR Lower Nibble Configura- to SCLOUT. Connect a pull-up resistor, typically 10k, from
tion Input. The DC voltage at this pin configures the lower this pin to the bus pull-up supply. Leave open or tie to
4-bit nibble of the address translation byte. Tie the pin to GND if unused.
an external resistive divider connected between VCC and
GND to set the desired DC voltage.
SCLIN1/SCLIN2: Input Bus Clock Input and Output. Con-
nect this pin to the SCL line on the master side. An external
XORH1/XORH2: Translator XOR Upper Nibble Configura- pull-up resistor or current source is required. Connect to
tion Input. The DC voltage at this pin configures the upper
3-bit nibble of the address translation byte. Tie the pin to
an external resistive divider connected between VCC and
GND to set the desired DC voltage. Connect this pin to VCC
to activate pass-through mode. See Application Informa-
tion section for more details.
VCC through a pull-up resistor if unused.
SCLOUT1/SCLOUT2: Output Bus Clock Input and Output.
Connect this pin to the SCL line on the slave side. An external
pull-up resistor or current source is required. Connect to
VCC through a pull-up resistor if unused.
ENABLE1/ENABLE2: Enable Input. If ENABLE pin is low,
the address translation is disabled, SDAIN is disconnected
from SDAOUT, and SCLIN is disconnected from SCLOUT.
A low to high transition on ENABLE restarts the configura-
SDAIN1/SDAIN2: Input Bus Data Input and Output. Connect
this pin to the SDA line on the master side. An external
pull-up resistor or current source is required. Connect to
VCC through a pull-up resistor if unused.
tion of the address translation byte and also enables the SDAOUT1/SDAOUT2: Output Bus Data Input and Output.
address translation. Connect to VCC if unused.
Exposed Pad: Exposed pad may be left open or connected
to device GND.
Connect this pin to the SDA line on the slave side. An
external pull-up resistor or current source is required.
Connect to VCC through a pull-up resistor if unused.
GND: Device Ground.
VCC: Power Supply Input (2.25V to 5.5V). If the supply
voltages for the input and output buses are different, con-
READY1/READY2: Ready Status Output. This is an open nect this pin to the lower supply. If the input and output
drain output to indicate that the device is ready for address supplies have the same nominal value and with tolerance
translation. The pin releases high when the LTC4318 has less than or equal to ±10%, connect VCC to either supply.
completed configuration of the address translation byte, Bypass with at least 0.1μF to GND.
SDAIN is connected to SDAOUT and SCLIN is connected
4318f
For more information www.linear.com/LTC4318
5
5 Page 
LTC4318
Operation
it may convert START bits to STOP bits and vice versa,
causing unexpected slave behavior.
If an START bit is received during the address byte when
the active translating bit is a "1", the slave device will see
a STOP bit. This will typically reset the slave and cause it
to miss the remainder of the transmission. If the START
bit is received while the active translating bit is a "0", the
START passes through the LTC4318 unchanged. The slave
will react in the same way it would if the LTC4318 was
not present, and will typically reset when the master next
issues a STOP bit. In both cases, the LTC4318 automati-
cally resets at the next STOP bit and the next message
will be transmitted normally.
If an STOP bit is received during the address byte, the
LTC4318 will abort the address translation and ensure that
a STOP bit is issued at SDAOUT to reset the slave. If the
active translating bit is a "0" when the STOP arrives, it is
not modified, and the slave will see the STOP and typically
reset. If the active translating bit is a "1" when the STOP
arrives, the slave device will see a START bit. This might
leave the slave in an indeterminate state, so the LTC4318
briefly disconnects the slave from the master, adds a short
delay, and then generates a STOP bit at the SDAOUT pin
(Figure 9). It then reconnects the busses and waits for a
START bit to begin the next transmission. Again, in both
cases, the LTC4318 automatically resets and the next
message will be transmitted normally.
Stuck Bus Timeout
During the address translation, if SCLIN stays low or high
for more than 30ms without any transitions, the LTC4318
will abort the address translation and reconnect SDAIN to
SDAOUT. It will then wait for a START bit to start a new
address translation. This prevents any bus stuck low/
high conditions from permanently disconnecting SDAIN
from SDAOUT.
Supported Protocols
The LTC4318 is designed to support most I2C and SMBus
message protocols. The only exceptions are protocols that
use pre-assigned addresses on the slave side of the bus.
Supported I2C and SMBus Protocols:
nn Send/Receive Byte
nn Write Byte/Word
nn Read Byte/Word
nn Process Call
nn Block Write/Read
nn Block Write-Block Read Process Call
nn Extended Read and Write Commands
nn General Call (I2C Only)
nn Start Byte (I2C Only)
ADDRESS BIT
BECOMES
STOP BIT
nn PMBus (without PEC)
Unsupported I2C Protocols:
SCLIN
SDAIN
STOP
BIT
START
BIT
TRANSLATION
BIT
SDAOUT
1
START
BIT
STOP
BIT
START
BIT
N2 GATE
N1 GATE
N2 OFF
N2 OFF
N1 ON
N2 ON
N1
OFF
N1 ON
4318 F09
Figure 9. Stop Bit within Address Byte when
Address Translation Byte Is 1
nn 10-Bit Addressing
nn Device ID
nn Ultra Fast-Mode I2C Bus Protocol
Unsupported SMBus Protocols:
nn SMBus Host Notify
nn Address Resolution Protocol (ARP)
nn Parity Error Code (PEC)
nn Alert Response Address (ARA)
nn PMBus (with PEC)
For more information www.linear.com/LTC4318
4318f
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet LTC4318.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LTC4310-1 | Hot-Swappable I2C Isolators |  Linear Technology |
| LTC4310-2 | Hot-Swappable I2C Isolators | Linear Technology |
| LTC4311 | Low Voltage I2C/SMBus Accelerator | Linear |
| LTC4315 | 2-Wire Bus Buffer | Linear |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |