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PDF SI5335 Data sheet ( Hoja de datos )
| Número de pieza | SI5335 | |
| Descripción | ANY-OUTPUT QUAD CLOCK GENERATOR/BUFFER | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si5335
WEB- C USTOMIZABLE, A NY- F REQUENCY, A NY- O UTPUT
QUAD CLOCK GENERATOR/BUFFER
Features
Low power MultiSynth™ technology Independent output voltage per driver:
enables independent, any-frequency
1.5, 1.8, 2.5, or 3.3 V
synthesis of four frequencies
Single supply core with excellent
Configurable as a clock generator or
PSRR: 1.8, 2.5, 3.3 V
clock buffer device
Up to five user-assignable pin
Three independent, user-assignable, pin- functions simplify system design:
selectable device configurations
SSENB (spread spectrum control),
Highly-configurable output drivers with
RESET, Master OEB or OEB per pin,
up to four differential outputs, eight
and Frequency plan select
single-ended clock outputs, or a
(FS1, FS0)
combination of both
Loss of signal alarm
Low phase jitter of 0.7 ps RMS
PCIe Gen 1/2/3/4 common clock
Flexible input reference:
compliant
External crystal: 25 or 27 MHz
PCIe Gen 3 SRNS Compliant
CMOS input: 10 to 200 MHz
Two selectable loop bandwidth
SSTL/HSTL input: 10 to 350 MHz
settings: 1.6 MHz or 475 kHz
Differential input: 10 to 350 MHz
Independently configurable outputs
support any frequency or format:
LVPECL/LVDS/CML: 1 to 350 MHz
HCSL: 1 to 250 MHz
CMOS: 1 to 200 MHz
SSTL/HSTL: 1 to 350 MHz
Easy to customize with web-based
utility
Small size: 4 x 4 mm, 24-QFN
Low power (core):
45 mA (PLL mode)
12 mA (Buffer mode)
Wide temperature range: –40 to
+85 °C
Applications
Ethernet switch/router
PCI Express Gen 1/2/3/4
PCIe jitter attenuation
DSL jitter attenuation
Broadcast video/audio timing
Processor and FPGA clocking
MSAN/DSLAM/PON
Fibre Channel, SAN
Telecom line cards
1 GbE and 10 GbE
Description
The Si5335 is a highly flexible clock generator capable of synthesizing four completely
non-integer-related frequencies up to 350 MHz. The device has four banks of outputs
with each bank supporting one differential pair or two single-ended outputs. Using
Silicon Laboratories' patented MultiSynth fractional divider technology, all outputs are
guaranteed to have 0 ppm frequency synthesis error regardless of configuration,
enabling the replacement of multiple clock ICs and crystal oscillators with a single
device. The Si5335 supports up to three independent, pin-selectable device
configurations, enabling one device to replace three separate clock generators or
buffer ICs. To ease system design, up to five user-assignable and pin-selectable
control pins are provided, supporting PCIe-compliant spread spectrum control, master
and/or individual output enables, frequency plan selection, and device reset. Two
selectable PLL loop bandwidths support jitter attenuation in applications, such as PCIe
and DSL. Through its flexible ClockBuilder™ (www.silabs.com/ClockBuilder) web
configuration utility, factory-customized, pin-controlled devices are available in two
weeks without minimum order quantity restrictions. Measuring PCIe clock jitter is quick
and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at
www.silabs.com/pcie-learningcenter.
Ordering Information:
See page 41.
Pin Assignments
Top View
24 23 22 21 20 19
XA/CLKIN 1
18 CLK1A
XB/CLKINB 2
17 CLK1B
P3 3
GND 4
GPGNaNdDD
16 VDDO1
15 VDDO2
P5 5
14 CLK2A
P6 6
13 CLK2B
7 8 9 10 11 12
Rev. 1.4 12/15
Copyright © 2015 by Silicon Laboratories
Si5335
1 page  
Si5335
Table 3. Performance Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
PLL Acquisition Time
PLL Tracking Range
tACQ
fTRACK
1.6 MHz loop bandwidth
475 kHz or 1.6 MHz loop
bandwidth
PLL Loop Bandwidth
MultiSynth Frequency
Synthesis Resolution
fBW1
fBW2
fRES
High bandwidth option
Low bandwidth option
Output frequency < Fvco/8
CLKIN Loss of Signal Detect
Time
tLOS
CLKIN Loss of Signal Release
Time
tLOSRLS
POR to Output Clock Valid
tRDY
Input-to-Output Propagation
Delay
tPROP
Buffer Mode
(PLL Bypass)
Reset Minimum Pulse Width
Output-Output Skew1
Spread Spectrum PP
Frequency Deviation2
tRESET
tDSKEW
SSDEV
FOUT > 5 MHz
FOUT = 100 MHz
Spread Spectrum Modulation
Rate3
SSDEV
FOUT = 100 MHz
Notes:
1. Outputs at integer-related frequencies and using the same driver format.
2. Default value is 0.5% down spread.
3. Default value is 31.5 kHz for PCI compliance.
Min Typ
——
5000 20000
— 1.6
— 475
00
— 2.6
0.01 0.2
——
— 2.5
——
——
— –0.45
30 31.5
Max
25
—
—
—
1
5
1
2
4
200
100
–0.5
33
Unit
ms
ppm
MHz
kHz
ppb
µs
µs
ms
ns
ns
ps
%
kHz
Rev. 1.4
5
5 Page 
Si5335
Table 8. Jitter Specifications, Clock Generator Mode (Loop Bandwidth = 1.6 MHz)1,2,3 (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Cycle-Cycle Jitter
Random Jitter
(12 kHz–20 MHz)
Deterministic Jitter
N = 10,000 cycles
JCC
Output MultiSynth
operated in integer or
—
fractional mode7
9 29 ps pk8
Output and feedback
RJ
MultiSynth in integer or —
0.7 1.5 ps RMS
fractional mode7
Output MultiSynth
operated in fractional
—
3 15 ps pk-pk
mode7
DJ
Output MultiSynth
operated in integer
— 2 10 ps pk-pk
mode7
Total Jitter
(12 kHz–20 MHz)
T(JS=eeDJN+o1t4ex9R) J
Output MultiSynth
operated in fractional
mode7
Output MultiSynth
operated in integer
mode7
—
—
13 36 ps pk-pk
12 20 ps pk-pk
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and
are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there
is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration
implements any single-ended output and any output is required to have jitter less than 2 ps rms, contact Silicon Labs
for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS
outputs have little to no effect upon jitter.
3. For best jitter performance, keep the single-ended clock input slew rates at pins 1 and 2 greater that 1.0 V/ns and the
differential clock input slew rates greater than 0.3 V/ns.
4. DJ for PCI and GbE is < 5 ps pp
5. Output MultiSynth in Integer mode.
6. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.
See AN562 for details. Jitter is mesured with the Intel Clock Jitter Tool, Ver.1.6.4.
7. For any output frequency > 10 MHz.
8. Measured in accordance with JEDEC standard 65.
9. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges.
10. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
11. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
Rev. 1.4
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SI5335.PDF ] | |
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