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PDF MTD1P40E Data sheet ( Hoja de datos )
| Número de pieza | MTD1P40E | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
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MTD1P40E
Preferred Device
Advance Information
Power MOSFET
1 Amp, 400 Volts
P−Channel DPAK
This high voltage MOSFET uses an advanced termination scheme
to provide enhanced voltage−blocking capability without degrading
performance over time. In addition this advanced high voltage
MOSFET is designed to withstand high energy in the avalanche and
commutation modes. The energy efficient design also offers a
drain−to−source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
http://onsemi.com
1 AMPERES
400 VOLTS
RDS(on) = 8 Ω
P−Channel
D
G
S
MARKING
DIAGRAM
4
12
3
Y
WW
T
CASE 369A
DPAK
STYLE 2
= Year
= Work Week
= MOSFET
YWW
T
1P40E
PIN ASSIGNMENT
4
Drain
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
© Semiconductor Components Industries, LLC, 2004
August, 2004 − Rev. XXX
1
1 23
Gate Drain Source
ORDERING INFORMATION
Device
Package
Shipping
MTD1P40E
MTD1P40E1
DPAK
DPAK
75 Units/Rail
75 Units/Rail
MTD1P40ET4
DPAK 2500 Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
MTD1P40E/D
1 page  
MTD1P40E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
1000
VDS = 0 V VGS = 0 V
800
Ciss
600
TJ = 25°C
400 Crss
Ciss
200 Coss
0
−10 −5
Crss
05
10 15 20 25
VGS VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
http://onsemi.com
5
5 Page 
MTD1P40E
PACKAGE DIMENSIONS
DPAK
CASE 369A−13
ISSUE AA
B
VR
−T−
SEATING
PLANE
C
E
S
F
4
1 23
A
K
J
LH
D 2 PL
G 0.13 (0.005) M T
U
Z
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
INCHES
DIM MIN MAX
A 0.235 0.250
B 0.250 0.265
C 0.086 0.094
D 0.027 0.035
E 0.033 0.040
F 0.037 0.047
G 0.180 BSC
H 0.034 0.040
J 0.018 0.023
K 0.102 0.114
L 0.090 BSC
R 0.175 0.215
S 0.020 0.050
U 0.020 −−−
V 0.030 0.050
Z 0.138 −−−
MILLIMETERS
MIN MAX
5.97 6.35
6.35 6.73
2.19 2.38
0.69 0.88
0.84 1.01
0.94 1.19
4.58 BSC
0.87 1.01
0.46 0.58
2.60 2.89
2.29 BSC
4.45 5.46
0.51 1.27
0.51 −−−
0.77 1.27
3.51 −−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
http://onsemi.com
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MTD1P40E.PDF ] | |
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