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Número de pieza | TK55D10J1 | |
Descripción | Silicon N Channel MOS Type Field Effect Transistor | |
Fabricantes | Toshiba Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de TK55D10J1 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
No Preview Available ! TK55D10J1
TOSHIBA Field Effect Transistor Silicon N Channel MOS Type (Ultra-High-Speed U-MOSⅢ)
TK55D10J1
Switching Regulator Applications
• High-Speed switching
• Low gate charge: Qg = 110 nC (typ.)
• Low drain-source ON resistance: RDS (ON) = 8.4 mΩ (typ.)
• High forward transfer admittance: |Yfs| = 110 S (typ.)
• Low leakage current: IDSS = 10 μA (max) (VDS = 100 V)
• Enhancement mode: Vth = 1.1 to 2.3 V (VDS = 10 V, ID = 1 mA)
Absolute Maximum Ratings (Ta = 25°C)
Unit: mm
10.0±0.3
9.5±0.2
A
Ф3.65±0.2
0.6±0.1
1.1±0.15
0.75±0.25
Characteristics
Drain-source voltage
Drain-gate voltage (RGS = 20 kΩ)
Gate-source voltage
Drain current
DC (Note 1)
Pulse (Note 1)
Drain power dissipation (Tc = 25°C)
Single pulse avalanche energy
(Note 2)
Avalanche current
Repetitive avalanche energy (Note 3)
Channel temperature
Storage temperature range
Symbol
VDSS
VDGR
VGSS
ID
IDP
PD
EAS
IAR
EAR
Tch
Tstg
Rating
100
100
±20
55
210
140
382
55
9.4
150
−55 to 50
Unit
V
V
V
A
W
mJ
A
mJ
°C
°C
0.62±0.15
Ф0.2 M A
2.54
2.54
0.57+-00..2105
2.53±0.2
123
1: Gate
2: Drain (Heat Sink)
3: Source
JEDEC
-
JEITA
-
TOSHIBA
2-10V1A
Weight: 1.35 g (typ.)
Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability
Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e.
reliability test report and estimated failure rate, etc).
Thermal Characteristics
Characteristics
Symbol
Max Unit
Thermal resistance, channel to case
Thermal resistance, channel to ambient
Rth (ch-c)
Rth (ch-a)
0.89
83.3
°C/W
°C/W
Note 1: Ensure that the channel and lead temperatures do not exceed 150°C.
Note 2: VDD = 25 V, Tch = 25°C, L = 200 μH, IAR = 55 A , RG = 1Ω
Note 3: Repetitive rating: pulse width limited by maximum channel temperature
This transistor is an electrostatic-sensitive device. Handle with care.
Internal Connection
2
1
3
1 2009-09-29
1 page TK55D10J1
rth/Rth (ch-c) – tw
10
1
Duty=0.5
0.2
0.1
0.1 0.05
0.02
0.01
0.01
10μ
100μ
SINGLE PULSE
PDM
t
T
Duty = t/T
Rth (ch-c) = 0.89°C/W
1m
10m
100m
PULSE WIDTH tw (s)
1
10
SAFE OPERATING AREA
1000
ID max (PULSED) *
100 ID max
(CONTINUOUS)
100 μs *
1 ms *
10
DC OPERATION
Tc = 25°C
1
0.1
※ Single pulse Ta=25℃
Curves must be derated
linearly with increase in
temperature.
0.01
1
10
VDSS max
100
1000
DRAIN-SOURCE VOLTAGE VDS (V)
EAS – Tch
500
400
300
200
100
0
25 50 75 100 125 150
CHANNEL TEMPERATURE (INITIAL)
Tch (°C)
20 V
0V
BVDSS
IAR
VDD
VDS
TEST CIRCUIT
WAVE FORM
RG = 1Ω
VDD = 25 V, L = 200μH
ΕAS
=
1
2
⋅L ⋅I2
⋅
⎜⎜⎝⎛
BVDSS
BVDSS − VDD
⎟⎟⎠⎞
5 2009-09-29
5 Page |
Páginas | Total 6 Páginas | |
PDF Descargar | [ Datasheet TK55D10J1.PDF ] |
Número de pieza | Descripción | Fabricantes |
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