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PDF MB91360 Data sheet ( Hoja de datos )
| Número de pieza | MB91360 | |
| Descripción | 32-BIT MICROCONTROLLER | |
| Fabricantes | Fujitsu Media Devices | |
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FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
CM71-10104-6EA
FR50
32-BIT MICROCONTROLLER
MB91360 Series
HARDWARE MANUAL
1 page  
MB91360 HARDWARE MANUAL
PREFACE
PREFACE
I Objectives and Intended Readership
The MB91360 was developed as a product in the FR50 series of 32-bit, single-chip
microcontrollers. The MB91360 contains a RISC architecture CPU core and is suitable for
embedded applications requiring a high level of CPU processing power.
This manual describes the functions and operation of the MB91360 and is written for engineers
who are developing actual products using MB91360 family products. Refer to the "FR Family
Instruction Manual"for further information on the MB91360 instruction set.
Note: FR: Fujitsu RISC
I Configuration of This Manual
This manual consists of the following chapters:
CHAPTER 1 MB91360 DESCRIPTION
This chapter provides an overview of the MB91360 and describes key information such as
the features, block diagram, and function description.
CHAPTER 2 CPU
This chapter describes key information about the functions of the FR50 series CPU core
including the architecture, specifications, and instructions.
CHAPTER 3 INSTRUCTION CACHE
This chapter describes the instruction cache memory included in MB91360 family members
and it operation. This only applies to MB91FV360GA.
CHAPTER 4 BOOT ROM / CONFIGURATION REGISTER
This chapter describes the functionality of the embedded boot ROM which is used in single
chip mode.
CHAPTER 5 CLOCK GENERATION AND DEVICE STATES
This chapter describes details about generation and control of the clock used to control the
MB91360. In addition device states and low power modes are explained. This chapter
assumes operation without subclock. For a description of subclock operation see the
corresponding chapter.
CHAPTER 6 CLOCK MODULATOR
This chapter provides an overview of the Clock Modulator and its features. It describes the
register structure and operation of the Clock Modulator.
CHAPTER 7 I/O PORTS
This chapter provides an overview of I/O ports, lists the registers, and describes conditions
for using external pins as I/O ports.
CHAPTER 8 EXTERNAL BUS INTERFACE
This Chapter describes in detail basic information about the external bus interface, the
register structure and functions, bus operation basics and bus timing.
i
5 Page 
MB91360 HARDWARE MANUAL
CONTENTS
CONTENTS
1 MB91360 DESCRIPTION ........................................................................................... 1
1.1 MB91360 FEATURES .............................................................................................................. 2
1.2 MB91360 PRODUCT LINEUP ................................................................................................. 4
1.3 PACKAGE DIMENSIONS ........................................................................................................ 8
1.4 MB91360 BLOCK STRUCTURE .............................................................................................. 9
1.5 PIN ASSIGNMENT ................................................................................................................. 17
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.7
1.5.8
1.5.9
Pin Diagram MB91FV360GA ................................................................................ 17
Pin Diagram MB91F362GB ................................................................................... 18
Pin Diagram MB91F364G ..................................................................................... 19
Pin Diagram MB91F369GA ................................................................................... 20
Pin Diagram MB91F365GB ................................................................................... 21
Pin Diagram MB91F366GB/MB91F376G ............................................................. 22
Pin Diagram MB91F367GB ................................................................................... 23
Pin Diagram MB91F368GB ................................................................................... 24
Pin Diagram MB91366GA ..................................................................................... 25
1.6 I/O PINS AND THEIR FUNCTION ......................................................................................... 26
1.6.1
1.6.2
1.6.3
1.6.4
1.6.5
1.6.6
1.6.7
MB91FV360GA I/O Pins and Their Function ........................................................ 26
MB91F362GB I/O Pins and Their Function ........................................................... 38
MB91F364G I/O Pins and Their Function ............................................................. 44
MB91F369GA I/O Pins and Their Function ........................................................... 48
MB91F365GB/F366GB/F376G, MB91366GA I/O Pins ......................................... 53
MB91F367GB/F368GB I/O Pins and Their Function ............................................ 57
I/O Circuit Type List ............................................................................................... 61
1.7 I/O CIRCUIT TYPES .............................................................................................................. 62
1.8 MEMORY SPACE .................................................................................................................. 70
1.9 HANDLING DEVICES ............................................................................................................ 71
2 CPU........................................................................................................................... 75
2.1 CPU ARCHITECTURE ........................................................................................................... 76
2.2 CPU HARDWARE STRUCTURE ........................................................................................... 78
2.3 INTERNAL ARCHITECTURE OF THE FR50 ......................................................................... 80
2.4 PROGRAMMING MODEL ...................................................................................................... 83
2.4.1
2.4.2
2.4.3
General-purpose Registers ................................................................................... 84
Dedicated Registers .............................................................................................. 85
Program Status Register (PS) ............................................................................... 88
2.5 DATA STRUCTURE ............................................................................................................... 92
2.5.1
Word Alignment ..................................................................................................... 93
2.6 MEMORY MAP ....................................................................................................................... 94
2.7 INSTRUCTIONS ..................................................................................................................... 96
2.7.1
2.7.2
Overview of Instructions and Basic Instructions .................................................... 97
Branch Instructions ............................................................................................. 101
2.8 EIT (EXCEPTIONS, INTERRUPT, TRAP) ........................................................................... 105
2.8.1
Multiple EIT Processing ...................................................................................... 111
vii
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