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PDF LTC2418 Data sheet ( Hoja de datos )
| Número de pieza | LTC2418 | |
| Descripción | 8-/16-Channel 24-Bit No Latency ADCs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC2414/LTC2418
8-/16-Channel
24-Bit No Latency ∆ΣTM ADCs
FEATURES
■ 8-/16-Channel Single-Ended or 4-/8-Channel
Differential Inputs (LTC2414/LTC2418)
■ Low Supply Current (200µA, 4µA in Autosleep)
■ Differential Input and Differential Reference
with GND to VCC Common Mode Range
■ 2ppm INL, No Missing Codes
■ 2.5ppm Full-Scale Error and 0.5ppm Offset
■ 0.2ppm Noise
■ No Latency: Digital Filter Settles in a Single Cycle
Each Conversion Is Accurate, Even After a New
Channel is Selected
■ Single Supply 2.7V to 5.5V Operation
■ Internal Oscillator—No External Components
Required
■ 110dB Min, 50Hz/60Hz Notch Filter
U
APPLICATIO S
■ Direct Sensor Digitizer
■ Weight Scales
■ Direct Temperature Measurement
■ Gas Analyzers
■ Strain Gauge Transducers
■ Instrumentation
■ Data Acquisition
■ Industrial Process Control
DESCRIPTIO
The LTC®2414/LTC2418 are 8-/16-channel (4-/8-differ-
ential) micropower 24-bit ∆Σ analog-to-digital convert-
ers. They operate from 2.7V to 5.5V and include an
integrated oscillator, 2ppm INL and 0.2ppm RMS noise.
They use delta-sigma technology and provide single cycle
settling time for multiplexed applications. Through a
single pin, the LTC2414/LTC2418 can be configured for
better than 110dB differential mode rejection at 50Hz or
60Hz ±2%, or they can be driven by an external oscillator
for a user-defined rejection frequency. The internal oscil-
lator requires no external frequency setting components.
The LTC2414/LTC2418 accept any external differential
reference voltage from 0.1V to VCC for flexible ratiometric
and remote sensing measurement applications. They can
be configured to take 4/8 differential channels or
8/16 single-ended channels. The full-scale bipolar input
range is from – 0.5VREF to 0.5VREF. The reference common
mode voltage, VREFCM, and the input common mode volt-
age, VINCM, may be independently set within GND to VCC.
The DC common mode input rejection is better than 140dB.
The LTC2414/LTC2418 communicate through a flexible
4-wire digital interface that is compatible with SPI and
MICROWIRETM protocols.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
TYPICAL APPLICATIO
2.7V TO 5.5V
THERMOCOUPLE
21 CH0
22 CH1
•
•
•
28 CH7
1 CH8
•
•
•
8 CH15
10 COM
16-CHANNEL
MUX
11 9
REF+ VCC
+ DIFFERENTIAL
– 24-BIT ∆Σ ADC
1µF
19
FO
VCC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
SDI 20
18
SCK
SDO 17
16
CS
4-WIRE
SPI INTERFACE
12 REF –
15 GND
LTC2418
241418 TA01a
Total Unadjusted Error
vs Input Voltage
3
VCC = 5V
VREF = 5V
2 VINCM = VREFCM = 2.5V
FO = GND
1
TA = 25°C
0
TA = –45°C
–1 TA = 85°C
–2
–3
–2.5 –2 –1.5 –1 –0.5 0 0.5 1.0 1.5 2.0 2.5
INPUT VOLTAGE (V)
2414/18 TA01b
241418fa
1
1 page  
LTC2414/LTC2418
DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
VOL
VOH
VOL
IOZ
PARAMETER
Low Level Output Voltage
SDO
High Level Output Voltage
SCK
Low Level Output Voltage
SCK
Hi-Z Output Leakage
SDO
CONDITIONS
IO = 1.6mA
IO = – 800µA (Note 10)
IO = 1.6mA (Note 10)
MIN
●
TYP MAX UNITS
0.4 V
● VCC – 0.5
V
● 0.4 V
● –10
10 µA
POWER REQUIRE E TS The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
VCC
ICC
PARAMETER
Supply Voltage
Supply Current
Conversion Mode
Sleep Mode
Sleep Mode
CONDITIONS
CS = 0V (Note 12)
CS = VCC (Note 12)
CS = VCC, 2.7V ≤ VCC ≤ 3.3V (Note 12)
MIN
● 2.7
●
●
TYP MAX UNITS
5.5 V
200 300
4 10
2
µA
µA
µA
WU
TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
fEOSC
tHEO
tLEO
tCONV
fISCK
DISCK
fESCK
tLESCK
tHESCK
tDOUT_ISCK
tDOUT_ESCK
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time
FO = 0V
FO = VCC
External Oscillator (Note 11)
Internal SCK Frequency
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
Internal SCK Duty Cycle
(Note 10)
External SCK Frequency Range
(Note 9)
External SCK Low Period
(Note 9)
External SCK High Period
(Note 9)
Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
External SCK 32-Bit Data Output Time (Note 9)
● 2.56
2000
● 0.25
390
● 0.25
390
● 130.86 133.53 136.20
● 157.03 160.23 163.44
● 20510/fEOSC (in kHz)
19.2
fEOSC/8
● 45
55
● 2000
● 250
● 250
● 1.64
1.67 1.70
● 256/fEOSC (in kHz)
● 32/fESCK (in kHz)
kHz
µs
µs
ms
ms
ms
kHz
kHz
%
kHz
ns
ns
ms
ms
ms
241418fa
5
5 Page 
W
FU CTIO AL BLOCK DIAGRA
VCC
GND
REF+
REF –
CH0
CH1
CH15
COM
•
•
•
MUX
IN+
IN–
–+
DIFFERENTIAL
3RD ORDER
∆Σ MODULATOR
LTC2414/LTC2418
AUTOCALIBRATION
AND CONTROL
INTERNAL
OSCILLATOR
FO
(INT/EXT)
DECIMATING FIR
ADDRESS
SERIAL
INTERFACE
SDI
SCK
SDO
CS
241418 F01
Figure 1
TEST CIRCUITS
SDO
1.69k
CLOAD = 20pF
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
241418 TA02
VCC
1.69k
SDO
CLOAD = 20pF
241418 TA03
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
APPLICATIO S I FOR ATIO
CONVERTER OPERATION
Converter Operation Cycle
The LTC2414/LTC2418 are multichannel, low power, delta-
sigma analog-to-digital converters with an easy-to-use
4-wire serial interface (see Figure 1). Their operation is made
up of three states. The converter operating cycle begins with
the conversion, followed by the low power sleep state and
ends with the data input/output (see Figure 2). The 4-wire
interface consists of serial data input (SDI), serial data out-
put (SDO), serial clock (SCK) and chip select (CS).
Initially, the LTC2414 or LTC2418 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. The part remains in the sleep state as long as
CS is HIGH. While in the sleep state, power consumption
is reduced by nearly two orders of magnitude. The conver-
sion result is held indefinitely in a static shift register while
the converter is in the sleep state.
Once CS is pulled LOW, the device exits the low power
mode and enters the data output state. If CS is pulled HIGH
before the first rising edge of SCK, the device returns to the
low power sleep mode and the conversion result is still
held in the internal static shift register. If CS remains LOW
after the first rising edge of SCK, the device begins output-
ting the conversion result and inputting channel selection
bits. Taking CS high at this point will terminate the data
output state and start a new conversion. The channel
selection control bits are shifted in through SDI from the
241418fa
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC2418.PDF ] | |
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