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PDF TLE8718SA Data sheet ( Hoja de datos )
| Número de pieza | TLE8718SA | |
| Descripción | Smart 18-Channel Lowside Switch | |
| Fabricantes | Infineon Technologies | |
| Logotipo |  |
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TLE 8718 SA
Smart 18-Channel Lowside Switch with Micro Second Bus
Data Sheet
Rev. 1.1, 2012-07-31
Automotive Power
1 page  
TLE 8718 SA
Overview
1.1 Device Description
All stages are controlled by MSC interface. The MSC interface can be single ended or low voltage differential type.
Serial transmission of the error code (diagnostic) via MSC interface (upstream channel).
All power stages (PS) are protected against short circuit to battery voltage (SCB). All PS (OUT1...18) are equipped
with switch off mode and current control mode in case of SCB (configurable).
Diagnosis of open load (OL), short-circuit to ground (SCG), short-circuit to battery voltage (SCB) and over
temperature (DOT) individually for each PS.
The fault conditions SCB, SCG, OL and DOT are not stored until an integrated filtering time has expired. If, at one
output, several errors occur in a sequence, always the last detected error is stored (after filtering time). All fault
conditions are encoded in two bits per stage and stored in the corresponding MSC interface registers. Additionally
there is one common diagnostic bit for fault occurrence (FAILURE_FLAG) at any output and one common
diagnostic bit (COTW) for diagnosis over temperature (DOT). The diagnostic registers can be read via MSC
interface. During the start-bit of a read out cycle the corresponding diagnostic register is cleared, nevertheless the
status of the diagnostic register before the start-bit is send. Pull-down Diagnostic currents and Open Load OL can
be switched off by configuration for OUT11...18; (CONREG3 and OUT1516).
Each stage (OUT1...14, 17, 18) is controlled with a separate bit of the data frame (downstream channel). The
control bit is non inverting, i.e. if a control bit is ‘1’ the corresponding stage is off. Stages are disabled – i.e. switched
off and switching on disabled if VDD is too low (VDD undervoltage or power on reset) or VDD too high (VDD
overvoltage). The same applies when the MSC monitoring detects an error, micro controller reset is active (i.e.
external signal on pin RST = low or external signal on Pin ABE is logical low level).
All outputs are designed with internal zener diodes for applications with inductive loads.
OUT1 and OUT3 are designed for normal operation with 4A and extended current of 8A for maximum of 200
seconds each vehicle driving cycle.
OUT5...OUT10 are disabled by active low level on pins DIS5_10 (with short delay).
OUT9 and OUT10 are designed for actuators with higher clamping energy.
OUT15 and OUT16 can be forced OFF with the higher thresholds of DELAYIN (VDELAYIN_RES15_16_L and
VDELAYIN_RES15_16_H) (see Figure 8). OUT15 and OUT16 can be configured to delayed reset behavior, in this case,
the switching-off algorithm is delayed by internal filtering time (exception: power on reset (POR), RES15_16 and
valid command frame to switch off stages is not delayed).
Parallel connection of stages (OUT1...14, 17, 18) is possible as the control bits that switch on and off these stages
are all transmitted in the same data frame. OUT15 and OUT16 are only allowed to be connected to each other
and not to other stages (see Chapter 5.10).
DELAYOUT is pulled active low to switch off external components by the lower thresholds of DELAYIN (VDELAYIN_L
and VDELAYIN_H), ABE or VDD monitoring.
Data Sheet
5 Rev. 1.1, 2012-07-31
5 Page 
TLE 8718 SA
General Product Characteristics
4 General Product Characteristics
4.1 Test coverage (TC) in series production
In the standard production flow not all parameters can be covered due to technical or economic reasons. Therefore
the following test coverage classes are defined:
A) Parameter test (parameter is measured in production test)
B) Go/NoGo test (parameter within specified range is guaranteed by Go/NoGo-test in production)
C) Specified by design (covered by lab tests, not considered within the standard production flow)
The given supply voltage range is only valid as long as the related function is active. (e.g. the power stages are
shut off if VBAT > 28V. In that case, no function is available to be tested at VBAT = 40V).
4.2 Absolute Maximum Ratings
The integrated circuit will not be damaged if maximum ratings are reached. Every maximum rating is allowed to
be reached at the same time, as long as no other maximum rating is exceeded. But see Item Note:
Unless otherwise indicated all voltages are referred to PGND (all PGND and GNDABE are externally connected
to each other) Positive current flows into the pin.
Table 3 Maximum Ratings
Tj = -40°C to +150°C, all voltages with respect to PGND, positive current flowing into pin, unless otherwise
specified
Pos. Parameter
Symbol
Values Unit TC Conditions
min. max.
Supply and Power Pins
4.2.1 Supply Voltage Range
pin VDD, static
VDD_MR
-0.3 36 V C –
4.2.2 Battery Voltage
stages output pins via load
VBAT_MR
-1 40 V C –
4.2.3 Total current over the PGND
4.2.4 Ground Voltage Offset
maximum permissible offset
between GNDABE and the PGND
IPGND_MR
dVGND_MR
-38 38 A C –
-0.3 0.3 V C –
4.2.5 Output Stages
static voltage OUTn (n=1...18)
VOUTn_MR
-0.3 50 V C OUTn OFF
4.2.6 Short Circuit to VBAT
(single event)
VBAT_SC
-0.3 36 V C OUTn (n=1...18),
Figure 4
Interface and Logic
4.2.7 Logic Input Pins
SIP, SIN, SI,
FCLP, FCLN, FCL,
SSY, DIS5_10, RST
4.2.8 Bidirectional Pin ABE
4.2.9 Output Pins
DELAYOUT, SDO
V VSIP_MR, SIN_MR,
V VSI_MR, FCLP_MR,
V VFCLN_MR, FCL_MR,
V VSSY_MR, DIS5_10_MR,
VRST_MR
VABE_MR
VDELAYOUT_MR,
VSDO_MR
-0.3
-0.3
-0.3
36
36
36
V C–
V C–
V C–
Data Sheet
11 Rev. 1.1, 2012-07-31
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TLE8718SA.PDF ] | |
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