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PDF MPC5200 Data sheet ( Hoja de datos )

Número de pieza MPC5200
Descripción Users Guide
Fabricantes Freescale Semiconductor　
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No Preview Available ! MPC5200 Hoja de datos, Descripción, Manual

MPC5200 Users Guide
Document Number: MPC5200UG
Rev. 3.1
03/2006

1 page




MPC5200 pdf
Paragraph
Number
7.1
7.2
7.2.1
7.2.1.1
7.2.1.2
7.2.1.3
7.2.2
7.2.3
7.2.4
7.2.4.1
7.2.4.2
7.2.4.3
7.2.4.4
7.2.4.5
7.2.4.6
7.2.4.7
7.2.4.8
7.2.4.9
7.2.4.10
7.2.4.11
7.2.4.12
7.2.4.13
7.2.4.14
7.2.4.15
7.2.4.16
7.3
7.3.1
7.3.1.1
7.3.1.2
7.3.1.3
7.3.1.4
7.3.1.5
7.3.1.6
7.3.1.7
7.3.1.8
7.3.1.9
7.3.2
7.3.2.1
7.3.2.1.1
7.3.2.1.2
7.3.2.1.3
7.3.2.1.4
7.3.2.1.5
7.3.2.1.6
7.3.2.1.7
7.3.2.1.8
7.3.2.1.9
7.3.2.1.10
7.3.2.1.11
7.3.2.1.12
7.3.2.1.13
7.3.2.1.14
7.3.2.1.15
Table of Contents
Page
Number
Chapter 7 System Integration Unit (SIU)
Overview ...................................................................................................................................................................7-1
Interrupt Controller ....................................................................................................................................................7-1
Block Description ...............................................................................................................................................7-1
Machine Check Pin—core_mcp ...................................................................................................................7-2
System Management Interrupt—core_smi ...................................................................................................7-2
Standard Interrupt—core_int ........................................................................................................................7-2
Interface Description ...........................................................................................................................................7-4
Programming Note ..............................................................................................................................................7-4
Interrupt Controller Registers .............................................................................................................................7-5
ICTL Peripheral Interrupt Mask Register—MBAR + 0x0500 .....................................................................7-5
ICTL Peripheral Priority and HI/LO Select 1 Register —MBAR + 0x0504 ..............................................7-7
ICTL Peripheral Priority and HI/LO Select 2 Register —MBAR + 0x0508 ..............................................7-8
ICTL Peripheral Priority and HI/LO Select 3 Register —MBAR + 0x050C ..............................................7-8
ICTL External Enable and External Types Register —MBAR + 0x0510 ...................................................7-9
ICTL Critical Priority and Main Interrupt Mask Register—MBAR + 0x0514 ..........................................7-10
ICTL Main Interrupt Priority and INT/SMI Select 1 Register —MBAR + 0x0518 .................................7-12
ICTL Main Interrupt Priority and INT/SMI Select 2 Register—MBAR + 0x051C ..................................7-13
ICTL Perstat, MainStat, MainStat, CritStat Encoded Register—MBAR + 0x0524 ..................................7-14
ICTL Critical Interrupt Status All Register—MBAR + 0x0528 ................................................................7-15
ICTL Main Interrupt Status All Register—MBAR + 0x052C ...................................................................7-16
ICTL Peripheral Interrupt Status All Register—MBAR + 0x0530 ............................................................7-17
ICTL Peripheral Interrupt Status All Register—MBAR + 0x0538 ............................................................7-18
ICTL Main Interrupt Emulation All Register—MBAR + 0x0540 .............................................................7-19
ICTL Peripheral Interrupt Emulation All Register—MBAR + 0x0544 .....................................................7-20
ICTL IRQ Interrupt Emulation All Register—MBAR + 0x0548 ..............................................................7-21
General Purpose I/O (GPIO) ..................................................................................................................................7-21
GPIO Pin Multiplexing .....................................................................................................................................7-24
PSC1 (UART1/AC97/CODEC1) .............................................................................................................7-25
PSC2 (CAN1/2/UART2/AC97/CODEC2) ...............................................................................................7-25
PSC3 (USB2/CODEC3/SPI/UART3) .....................................................................................................7-25
USB1/RST_CONFIG .................................................................................................................................7-25
Ethernet/USB2/UART4/5/J1850/RST_CONFIG .....................................................................................7-25
PSC6 ...........................................................................................................................................................7-26
I2C ...............................................................................................................................................................7-26
GPIO Timer Pins ........................................................................................................................................7-26
Dedicated GPIO Port ..................................................................................................................................7-27
GPIO Programmer’s Model ..............................................................................................................................7-27
GPIO Standard Registers—MBAR+0x0B00 ............................................................................................7-27
GPS Port Configuration Register—MBAR + 0x0B00 ........................................................................7-28
GPS Simple GPIO Enables Register—MBAR + 0x0B04 ...................................................................7-31
GPS Simple GPIO Open Drain Type Register —MBAR + 0x0B08 ...................................................7-32
GPS Simple GPIO Data Direction Register—MBAR + 0x0B0C .......................................................7-33
GPS Simple GPIO Data Output Values Register —MBAR + 0x0B10 ...............................................7-36
GPS Simple GPIO Data Input Values Register —MBAR + 0x0B14 ..................................................7-37
GPS GPIO Output-Only Enables Register —MBAR + 0x0B18 .........................................................7-38
GPS GPIO Output-Only Data Value Out Register —MBAR + 0x0B1C ............................................7-39
GPS GPIO Simple Interrupt Enable Register—MBAR + 0x0B20 ......................................................7-40
GPS GPIO Simple Interrupt Open-Drain Emulation Register —MBAR + 0x0B24 ...........................7-40
GPS GPIO Simple Interrupt Data Direction Register —MBAR + 0x0B28 ........................................7-41
GPS GPIO Simple Interrupt Data Value Out Register —MBAR + 0x0B2C ......................................7-42
GPS GPIO Simple Interrupt Interrupt Enable Register —MBAR + 0x0B30 ......................................7-42
GPS GPIO Simple Interrupt Interrupt Types Register —MBAR + 0x0B34 .......................................7-43
GPS GPIO Simple Interrupt Master Enable Register —MBAR + 0x0B38 .........................................7-44
Freescale Semiconductor
MPC5200 Users Guide, Rev. 3.1
TOC-3

5 Page





MPC5200 arduino
Paragraph
Number
11.3.3.5
11.3.3.6
11.3.3.7
11.3.3.8
11.3.3.9
11.3.3.10
11.3.3.11
11.3.3.12
11.4
11.4.1
11.4.2
11.4.2.1
11.5
11.6
11.7
11.7.1
11.7.2
11.7.3
11.7.31
11.7.3.2
11.7.3.3
11.7.3.4
11.7.4
11.7.4.1
11.7.4.1.1
11.7.4.1.2
11.7.4.1.3
11.7.4.2
11.7.4.3
11.7.4.3.1
11.7.4.4
11.8
11.8.1
11.8.2
11.9
12.1
12.2
12.3
12.3.1
12.3.2
12.4
12.4.1
12.4.2
12.4.2.1
12.4.2.2
12.4.2.3
12.4.2.4
12.4.2.5
12.4.2.6
12.4.3
12.4.3.1
Table of Contents
Page
Number
ATA Drive Error Register—MBAR + 0x3A64 .......................................................................................11-14
ATA Drive Sector Count Register—MBAR + 0x3A68 ...........................................................................11-15
ATA Drive Sector Number Register—MBAR + 0x3A6C .......................................................................11-15
ATA Drive Cylinder Low Register—MBAR + 0x3A70 .........................................................................11-16
ATA Drive Cylinder High Register—MBAR + 0x3A74 .........................................................................11-16
ATA Drive Device/Head Register—MBAR + 0x3A78 ..........................................................................11-17
ATA Drive Device Command Register—MBAR + 0x3A7C ..................................................................11-17
ATA Drive Device Status Register—MBAR + 0x3A7C .........................................................................11-19
ATA Host Controller Operation ............................................................................................................................11-20
PIO State Machine ..........................................................................................................................................11-21
DMA State Machine .......................................................................................................................................11-22
Software Requirements .............................................................................................................................11-22
Signals and Connections .......................................................................................................................................11-23
ATA Interface Description ....................................................................................................................................11-24
ATA Bus Background ...........................................................................................................................................11-26
Terminology ....................................................................................................................................................11-26
ATA Modes ....................................................................................................................................................11-27
ATA Addressing .............................................................................................................................................11-27
ATA Register Addressing ........................................................................................................................11-28
Drive Interrupt ..........................................................................................................................................11-28
Sector Addressing .....................................................................................................................................11-28
Physical/Logical Addressing Modes ........................................................................................................11-29
ATA Transactions ...........................................................................................................................................11-30
PIO Mode Transactions ............................................................................................................................11-30
Class 1—PIO Read ............................................................................................................................11-30
Class 2—PIO Write ............................................................................................................................11-31
Class 3—Non-Data Command ...........................................................................................................11-32
DMA Protocol ..........................................................................................................................................11-32
Multiword DMA Transactions .................................................................................................................11-35
Class 4—DMA Command .................................................................................................................11-35
Ultra DMA Protocol .................................................................................................................................11-35
ATA RESET/Power-Up .......................................................................................................................................11-36
Hardware Reset ...............................................................................................................................................11-36
Software Reset ................................................................................................................................................11-36
ATA I/O Cable Specifications ..............................................................................................................................11-37
Chapter 12 Universal Serial Bus (USB)
Overview .................................................................................................................................................................12-1
Data Transfer Types ................................................................................................................................................12-1
Host Controller Interface .........................................................................................................................................12-2
Communication Channels .................................................................................................................................12-2
Data Structures ..................................................................................................................................................12-2
Host Control (HC) Operational Registers ...............................................................................................................12-5
Programming Note ............................................................................................................................................12-5
Control and Status Partition—MBAR + 0x1000 ..............................................................................................12-6
USB HC Revision Register—MBAR + 0x1000 ........................................................................................12-6
USB HC Control Register—MBAR + 0x1004 ..........................................................................................12-6
USB HC Command Status Register—MBAR + 0x1008 ...........................................................................12-8
USB HC Interrupt Status Register —MBAR + 0x100C ............................................................................12-9
USB HC Interrupt Enable Register—MBAR + 0x1010 .........................................................................12-10
USB HC Interrupt Disable Register—MBAR + 0x1014 .........................................................................12-11
Memory Pointer Partition—MBAR + 0x1018 ...............................................................................................12-12
USB HC HCCA Register—MBAR + 0x1018 .........................................................................................12-13
Freescale Semiconductor
MPC5200 Users Guide, Rev. 3.1
TOC-9

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