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PDF LQ121X3LG02 Data sheet ( Hoja de datos )
| Número de pieza | LQ121X3LG02 | |
| Descripción | TFT LCD Module | |
| Fabricantes | Sharp | |
| Logotipo |  |
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1 page  
LD-22906A -4
4. Input Terminals
4-1. TFT-LCD panel driving
CN1 (LVDS signals and +3.3V DC power supply))
Pin No.
Symbol
Function
1 Vcc +3.3V power supply
2 Vcc +3.3V power supply
3 GND
4 GND
5
RxIN0-
Receiver signal of LVDS CH0 (-)
6
RxIN0+
Receiver signal of LVDS CH0 (+)
7 GND
8
RxIN1-
Receiver signal of LVDS CH1 (-)
9
RxIN1+
Receiver signal of LVDS CH1 (+)
10 GND
11
RxIN2-
Receiver signal of LVDS CH2 (-)
12
RxIN2+
Receiver signal of LVDS CH2 (+)
13 GND
14
CK IN-
Receiver signal of LVDS CLK (-)
15
CK IN+
Receiver signal of LVDS CLK (+)
16 GND
17 NC
18 NC
19 GND
Remark
[Note 4-1]
[Note 4-1]
[Note 4-1]
[Note 4-1]
[Note 4-1]
[Note 4-1]
[Note 4-1]
[Note 4-1]
[Note 4-2]
[Note 4-2]
20 GND
[Note 4-1] Relation between RxINi(i=0,1,2) and actual data is shown in following section (4-2)(7-2).
[Note 4-2] Please use NC by OPEN or GND. NC terminal is not connected with the internal circuit.
Using connector : DF19L-20P-1H (HIROSE) or equivalent.
Corresponding connector : DF19G-20S-1C(HIROSE)
(Sharp is not responsible to its product quality, if the user applies a connector not corresponding to the
above model.)
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5 Page 
6-3. LVDS input specification
6-3-1. AC characteristics
Parameter
Input Data Position 0 (tRCIP=15.38ns)
Input Data Position 1 (tRCIP=15.38ns)
Input Data Position 2 (tRCIP=15.38ns)
Input Data Position 3 (tRCIP=15.38ns)
Input Data Position 4 (tRCIP=15.38ns)
Input Data Position 5 (tRCIP=15.38ns)
Input Data Position 6 (tRCIP=15.38ns)
Phase Lock Loop Set
Input Clock Period
LD-22906A -10
Symbol
Vcc=+3.0V～+3.6V，Ta＝-20 oC～+60 oC
Min
Typ.
Max.
Unit
tRIPI -0.25
0.0
+0.25
ns
tRIP0
tRIP6
tRCIP/7-0.25
2 tRCIP/7-0.25
tRCIP/7
2 tRCIP/7
tRCIP/7+0.25
2 tRCIP/7+0.25
ns
ns
tRIP5
tRIP4
3 tRCIP/7-0.25
4 tRCIP/7-0.25
3 tRCIP/7
4 tRCIP/7
3 tRCIP/7+0.25
4 tRCIP/7+0.25
ns
ns
tRIP3 5 tRCIP/7-0.25 5 tRCIP/7 5 tRCIP/7+0.25 ns
tRIP2 6 tRCIP/7-0.25 6 tRCIP/7 6 tRCIP/7+0.25 ns
tRPLL
－
－
10 ms
tRCIP
14.9
15.4
20 ns
LVDS input timing
tRIP2
tRIP3
tRIP4
tRIP5
tRIP6
tRIP0
tRIP1
RxINi+/-
RxINi6 RxINi5 RxINi4 RxINi3 RxINi2 RxINi1 RxINi0 RxINi6 RxINi5 RxINi4 RxINi3 RxINi2 RxINi1
CK IN+/-
i=0,1,2
LVDS phase lock loop set
VCC
3.0
CK IN+/-
PLLCLK
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Vdiff=0
tRCIP
Vdiff=0
※Note
Vdiff=(RxINi+)-(RxINi-)，(CK IN+)-(CK IN-)
Vdiff=0V
tRPLL
2.0
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| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet LQ121X3LG02.PDF ] | |
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