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PDF HD74CDCV857 Data sheet ( Hoja de datos )
| Número de pieza | HD74CDCV857 | |
| Descripción | 2.5-V Phase-lock Loop Clock Driver | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HD74CDCV857
2.5-V Phase-lock Loop Clock Driver
ADE-205-335C (Z)
Preliminary
4th Edition
March 2000
Description
The HD74CDCV857 is a high-performance, low-skew, low-jitter, phase locked loop clock driver. It is
specifically designed for use with DDR (Double Data Rate) synchronous DRAMs.
Features
• Supports 60 MHz to 200 MHz operation range
• Distributes one differential clock input pair to ten differential clock outputs pairs
• Supports spread spectrum clock requirements meeting the PC100 SDRAM registered DIMM
specification
• External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input
• Supports 2.5V analog supply voltage (AVCC), and 2.5 V VDDQ
• No external RC network required
• Sleep mode detection
• 48pin TSSOP (Thin Shrink Small Outline Package)
1 page  
Logic Diagram
HD74CDCV857
PWRDWN 37
AVCC 16
Powerdown
and Test
Logic
CLK 13
CLK 14
FBIN 36
FBIN 35
PLL
3 Y0
2
Y0
5 Y1
6
Y1
10 Y2
9
Y2
20 Y3
19
Y3
22 Y4
23
Y4
46 Y5
47
Y5
44 Y6
43
Y6
39 Y7
40
Y7
29 Y8
30
Y8
27 Y9
26
Y9
32 FBOUT
33
FBOUT
Note: All inputs and outputs are associated with VDDQ = 2.5 V.
5
5 Page 
FBOUT
FBOUT
Yx
Yx
Yx
Yx
Yx'
Yx'
tsk
tsk
Figure 4 Output skew
HD74CDCV857
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet HD74CDCV857.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HD74CDCV857 | 2.5-V Phase-lock Loop Clock Driver | Hitachi Semiconductor |
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