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PDF APL3206 Data sheet ( Hoja de datos )
| Número de pieza | APL3206 | |
| Descripción | (APL3206/A/B) Li+ Charger Protection IC | |
| Fabricantes | ANPEC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de APL3206 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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APL3206/A/B
Li+ Charger Protection IC with Integrated P-MOSFET
Features
General Description
• Input Over-Voltage Protection
• Input Over-Current Protection
• Battery Over-Voltage Protection
• High Immunity of False Triggering
• High Accuracy Protection Threshold
• A Built-In P-MOSFET
• Thermal Shutdown Protection
• Compliance to IEC61000-4-2 (Level 4)
± 8kV (Contact Discharge)
± 15kV (Air Discharge)
• Available in a TDFN2x2-8 and TSOT-23-6A
Packages
• Lead Free and Green Devices Available
(RoHS Compliant)
Applications
• Cell Phones
Simplified Application Circuit
5V Adapter or USB
ACIN CHRIN
APL3206/A/B
GATDRV
OUT
GND VBAT
Li+
Battery
CHRIN
PMIC
GATDRV
ISENS
VBAT
The APL3206/A/B provides complete Li+ charger protec-
tion against input over-voltage, input over-current, and
battery over-voltage. When any of the monitored param-
eters are over the threshold, the IC removes the power
from the charging system by turning off an internal switch.
All protections also have deglitch time against false trig-
gering due to voltage spikes or current transients.
The APL3206/A/B integrates a P-MOSFET with the body
diode reverse protection to replace the external P-MOSFET
and Schottky diode for charger function of cell phone’s
PMIC. When the CHRIN voltage drops below VBAT+20mV,
the internal power select circuit will reverse the body
diode’s terminal to prevent a reverse current flowing from
the battery back to CHRIN pin.
The APL3206/A/B provides complete Li+ charger protec-
tions and saves the external MOSFET and Schottky diode
for the charger of cell phone’s PMIC. The above features
and small package make the APL3206/A/B an ideal part
for cell phones applications.
Pin Configuration
ACIN 1
8 OUT
ACIN 2
7 OUT
GND 3 EP 6 CHRIN
VBAT 4
5 GATDRV
TDFN2x2-8
(Top View)
EP = Exposed Pad (connected to ground
plane for better heat dissipation)
OUT 1
CHRIN 2
GATDRV 3
TSOT-23-6A
(Top View)
6 VIN
5 GND
4 VBAT
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
1
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
1 page  
APL3206/A/B
Typical Operating Characteristics
Input OVP Threshold vs. Junction
Temperature
6.25
6.15
6.05
VACIN Increasing
5.95
5.85
5.75
VACIN Decreasing
5.65
-50
4.40
-25 0 25 50 75 100
Junction Temperature (oC)
Battery OVP Threshold vs.
Junction Temperature
125
4.35
4.30
VBAT Increasing
4.25
4.20
4.15
4.10
4.05
4.00
-50
VBAT Decreasing
-25 0 25 50 75 100 125
Junction Temperature (oC)
ACIN Supply Current vs.
Junction Temperature
-50 -25 0 25 50 75 100 125
Junction Temperature (oC)
Copyright © ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
5
OCP Threshold vs. Junction
Temperature
1.30
1.25
1.20
1.15
1.10
1.05
1.00
-50 -25
0
25 50 75 100 125
Junction Temperature (oC)
ACIN to OUT On Resistance vs.
Junction Temperature
1000
900
800
ACIN to OUT On Resistance
700
600
500
400
300
-50 -25 0 25 50 75 100 125
Junction Temperature (oC)
POR Threshold vs. Junction
Temperature
2.8
VACIN Increasing
2.7
2.6
2.5
2.4
VACIN Decreasing
2.3
2.2
-50
-25 0 25 50 75 100
Junction Temperature (oC)
125
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
5 Page 
APL3206/A/B
Function Description (Cont.)
VACIN
VPOR
VCHRIN -VBAT = 150mV
VOVP
VCHRIN -VBAT = 150mV
VCHRIN
VOUT
GATDRV is pulled low
P-MOS Gate
Control
Turn Off Internal
P-MOSFET
TB(ACIN)
Controlled
by GATDRV
Turn Off Internal P-MOSFET
ACIN OVP
TON(OVP)
Figure 1. OVP Timing Diagram
Controlled by
GATDRV
IOCP
IOUT
GATDRV is pulled low
VCHRIN
P-MOS Gate Controlled by
Control
GATDRV
Turn Off Internal
P-MOSFET
TB(OCP)
TON(OCP)
Controlled by
GATDRV
Turn Off
Internal P-
MOSFET
TB(OCP)
Count 13
times
Controlled Turn Off
by Internal P-
GATDRV MOSFET
Total count 16
TB(OCP)
times, IC is
latched off
Figure 2. OCP Timing Diagram
Copyright © ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
11
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet APL3206.PDF ] | |
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