PDF PG12864LRU-ORA-H-S0 Data sheet ( Hoja de datos )

Número de pieza	PG12864LRU-ORA-H-S0
Descripción	LCD Module
Fabricantes	Powertip
Logotipo
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No Preview Available ! POWERTIP TECH. CORP. DISPLAY DEVICES FOR BETTER ELECTRONIC DESIGN Specification For Approval Customer Model Type Sample Code Mass Production Code Edition LCD Module PG12864LRU-ORA-H-S0 0 Customer Sign Sales Sign Approved By Prepared By NO.PT-R-003-4 Free Datasheet http:// 1 page NO.PG12864LRU-ORA-H Rev:0 1.6 Backlight Characteristic The LCD Module is backlight using a LED panel •.Maximum Ratings Item Forward current Reverse voltage Power dissipation Operating Temperature Storage temperature Symbol IF VR PO TOPR TSTG Conditions TA=25°C TA=25°C TA=25°C - - Min. - - - -20 -40 Max. 200 8 0.92 70 80 Unit mA V W °C °C •.Electrical Ratings Item Symbol Forward voltage VF Reverse current IR Luminous intensity* IV Wavelength HUE Color Yellow Green *Used BM-8 tester ,high=300mm Condition Min. Typ. Max. IF=80mA 4.0 4.2 4.6 VR=8V - - 0.2 IF=80mA 9.6 12.0 IF=80mA 569 - 576 Unit V mA cd/m2 nm 4.2V 17 LCD 18 MODULE POWERTIP TECHNOLOGY CORPORATION DISPLAY DEVICES FOR BETTER ELECTRONIC DESIGN Free Datasheet http://www.datasheet4u.com/ 5 Page 2-3.2 Serial Interface Timing tDSS CSB NO.PG12864LRU-ORA-H Rev:0 tCSH RS SCL tSLW tASS tDSS tSHW tDHS tAHS SDA tCYCS Item Serial clock period SCL “H” pulse width SCL “L” pulse width Address setup time Address hold time Data set up time Data hold time DSB to SCL time CSB hold time Input signal rise and fall time Symbol tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH tr,tf Mesauring condition (VDD=2.4~5.5V,Ta=-30 to +85 ) MIN MAX Unit Appllcable pin 1000 ns SCL 400 ns 400 ns 80 ns RS 80 ns 400 SDA 400 ns 80 ns CSB 80 ns 30 ns All of above pins (VDD=1.8~2.4V,Ta=-30 to +85 ) Item Symbol Mesauring condition MIN MAX Unit Appllcable pin Serial clock period tCYCS 2000 ns SCL SCL “H” pulse width tSHW 800 ns SCL “L” pulse width tSLW 800 ns Address setup time tASS 160 ns RS Address hold time tAHS 160 ns Data set up time tDSS 800 SDA Data hold time tDHS 800 ns DSB to SCL time tCSS 160 ns CSB CSB hold time tCSH 160 ns Input signal rise and fall time tr,tf 30 ns All of above pins Note: All the timings must be specified relative to 20% and 80% of VDD voltage. POWERTIP TECHNOLOGY CORPORATION DISPLAY DEVICES FOR BETTER ELECTRONIC DESIGN Free Datasheet http://www.datasheet4u.c 11 Page

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Hoja de datos destacado

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