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PDF SI536 Data sheet ( Hoja de datos )

Número de pieza SI536
Descripción (SI535 / SI536) ULTRA LOW JITTER CRYSTAL OSCILLATOR
Fabricantes Silicon Labs 
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Si535/536
REVISION D
ULTRA LOW JITTER CRYSTAL OSCILLATOR (XO)
Features
Available with select frequencies from Available with LVPECL and
100 MHz to 312.5 MHz
LVDS outputs
3rd generation DSPLL® with superior 3.3 and 2.5 V supply options
jitter performance and high-power Industry-standard 5 x 7 mm
supply noise rejection
package and pinout
3x better frequency stability than Pb-free/RoHS-compliant
SAW-based oscillators
Applications
10/40/100G data centers
10G Ethernet switches/routers
Fibre channel/SAS/storage
Enterprise servers
Networking
Telecommunications
Description
The Si535/536 XO utilizes Silicon Laboratories’ advanced DSPLL® circuitry
to provide an ultra low jitter clock at high-speed differential frequencies.
Unlike a traditional XO, where a different crystal is required for each output
frequency, the Si535/536 uses one fixed crystal to provide a wide range of
output frequencies. This IC based approach allows the crystal resonator to
provide exceptional frequency stability and reliability. In addition, DSPLL
clock synthesis provides superior supply noise rejection, simplifying the task
of generating low jitter clocks in noisy environments typically found in
communication systems. The Si535/536 IC based XO is factory programmed
at time of shipment, thereby eliminating long lead times associated with
custom oscillators.
Functional Block Diagram
VDD CLK– CLK+
Fixed
Frequency
XO
100–312.5 MHz
DSPLL®
Clock Synthesis
Si5602
Ordering Information:
See page 7.
Pin Assignments:
See page 6.
(Top View)
NC 1
6 VDD
OE 2
5 CLK–
GND 3
4 CLK+
Si535
OE 1
6 VDD
NC 2
5 CLK–
GND 3
4 CLK+
Si536
OE GND
Preliminary Rev. 0.6 7/13
Copyright © 2013 by Silicon Laboratories
Si535/536
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Free Datasheet http://www.datasheet4u.com/

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SI536 pdf
Si535/536
Table 6. Environmental Compliance
The Si535/536 meets the following qualification test requirements.
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross & Fine Leak
Resistance to Solder Heat
Moisture Sensitivity Level
Contact Pads
Conditions/Test Method
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2036
J-STD-020, MSL1
Gold over Nickel
Table 7. Thermal Characteristics
(Typical values TA = 25 ºC, VDD = 3.3 V)
Parameter
Symbol Test Condition Min Typ Max Unit
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
Ambient Temperature
Junction Temperature
JA
JC
TA
TJ
Still Air
Still Air
— 84.6 — °C/W
— 38.8 — °C/W
–40 —
85 °C
— — 125 °C
Table 8. Absolute Maximum Ratings1
Parameter
Symbol
Rating
Unit
Maximum Operating Temperature
TAMAX
85
°C
Supply Voltage, 2.5/3.3 V Option
VDD –0.5 to +3.8
V
Input Voltage (any input pin)
VI –0.5 to VDD + 0.3 V
Storage Temperature
TS –55 to +125 °C
ESD Sensitivity (HBM, per JESD22-A114)
ESD
2500
V
Soldering Temperature (Pb-free profile)2
Soldering Temperature Time @ TPEAK (Pb-free profile)2
TPEAK
tP
260
20–40
°C
seconds
Notes:
1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO for further information, including soldering profiles.
Preliminary Rev. 0.6
5

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SI536 arduino
Si535/536
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.3
Updated Table 7 on page 5.
Revision 0.3 to Revision 0.5
Updated Note 1 in Table 2 on page 2.
Updated Symmetry Test Condition in Table 3 on
page 3.
Updated Table 4 on page 4.
Updated Table 5 on page 4.
Updated XXXMXXX text in Figure 2 on page 7.
Updated 4. "Package Outline" on page 8.
Revision 0.5 to Revision 0.6
Updated Figure 2 on page 7.
Updated Land Pattern information on page 10.
11 Preliminary Rev. 0.6

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