|
|
PDF DAC1617D1G0 Data sheet ( Hoja de datos )
| Número de pieza | DAC1617D1G0 | |
| Descripción | Dual 16-bit DAC | |
| Fabricantes | IDT | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DAC1617D1G0 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
DAC1617D1G0
Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8
interpolating
Rev. 03 — 2 July 2012
Preliminary data sheet
1. General description
The DAC1617D1G0 is a high-speed 16-bit dual channel Digital-to-Analog Converter
(DAC) with selectable 2, 4 and 8 interpolation filters. The device is optimized for
multi-carrier and broadband wireless transmitters at sample rates of up to 1 Gsps.
Supplied from a 3.3 V and a 1.8 V source, the DAC1617D1G0 integrates a differential
scalable output current up to 34 mA.
The Serial Peripheral Interface (SPI) provides full control of the DAC1617D1G0.
The DAC1617D1G0 integrates a Low Voltage Differential Signaling (LVDS) Double Data
Rate (DDR) receiver interface, with an on-chip 100 termination. The LVDS DDR
interface accepts a multiplex input data stream such as interleaved or folded. An internal
LVDS input auto-calibration ensures the robustness and stability of the interface.
Digital on-chip modulation converts the complex I and Q inputs from baseband to IF. A
40-bit Numerically Controlled Oscillator (NCO) sets the mixer frequency. High resolution
internal gain, phase and offset control provide outstanding image and Local Oscillator
(LO) signal rejection at the system analog modulator output.
An inverse (sin x) / x function ensures a controlled flatness 0.5 dB for high bandwidths at
the DAC output.
http://www.DataSheet4U.net/
Multiple device synchronization allows synchronization of the outputs of multiple DAC
devices. MDS guarantees a maximum skew of one output clock period between several
devices.
The DAC1617D1G0 includes a very low noise capacitor-free integrated Phase-Locked
Loop (PLL) multiplier which generates a DAC clock rate from the LVDS clock rate.
The DAC1617D1G0 is available in an HVQFN72 package (10 mm 10 mm).
2. Features and benefits
Dual-channel 16-bit resolution
Synchronization of multiple DAC
devices
1 Gsps maximum update rate
3-wire or 4-wire mode SPI interface
Selectable 2, 4 and 8 interpolation Differential scalable output current from
filters
8.1 mA to 34 mA
Very low noise capacitor-free integrated External analog offset control
Phase-Locked Loop (PLL)
(10-bit auxiliary DACs)
®
datasheet pdf - http://www.DataSheet4U.net/
1 page  
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Table 2.
Symbol
LD[14]P
LD[14]N
VDDD
LD[13]P
LD[13]N
LD[12]P
LD[12]N
LD[11]P
LD[11]N
VDDD
LD[10]P
LD[10]N
LD[9]P
LD[9]N
LD[8]P
LD[8]N
VDDD
LCKP
LCKN
n.c.
LD[7]P
LD[7]N
LD[6]P
LD[6]N
LD[5]P
LD[5]N
VDDD
LD[4]P
LD[4]N
LD[3]P
LD[3]N
LD[2]P
LD[2]N
VDDD
LD[1]P
LD[1]N
LD[0]P
LD[0]N
IO1
IO0
SDO
Pin description …continued
Pin Type[1] Description
10 I
LVDS positive input bit 14[2]
11 I
LVDS negative input bit 14[2]
12 P
digital power supply
13 I
LVDS positive input bit 13[2]
14 I
LVDS negative input bit 13[2]
15 I
LVDS positive input bit 12[2]
16 I
LVDS negative input bit 12[2]
17 I
LVDS positive input bit 11[2]
18 I
LVDS negative input bit 11[2]
19 P
digital power supply
20 I
LVDS positive input bit 10[2]
21 I
LVDS negative input bit 10[2]
22 I
LVDS positive input bit 9[2]
23 I
LVDS negative input bit 9[2]
24 I
LVDS positive input bit 8[2]
25 I
LVDS negative input bit 8[2]
26 P
digital power supply
27 I
LVDS positive data clock input
28 I
LVDS negative data clock input
29 G
not connectedhttp://www.DataSheet4U.net/
30 I
LVDS positive input bit 7[2]
31 I
LVDS negative input bit 7[2]
32 I
LVDS positive input bit 6[2]
33 I
LVDS negative input bit 6[2]
34 I
LVDS positive input bit 5[2]
35 I
LVDS negative input bit 5[2]
36 P
digital power supply
37 I
LVDS positive input bit 4[2]
38 I
LVDS negative input bit 4[2]
39 I
LVDS positive input bit 3[2]
40 I
LVDS negative input bit 3[2]
41 I
LVDS positive input bit 2[2]
42 I
LVDS negative input bit 2[2]
43 P
digital power supply
44 I
LVDS positive input bit 1[2]
45 I
LVDS negative input bit 1[2]
46 I
LVDS positive input bit 0[2]
47 I
LVDS negative input bit 0[2]
48 IO IO port bit 1
49 IO IO port bit 0
50 O
SPI data output
DAC1617D1G0 3
Preliminary data sheet
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
5 of 78
datasheet pdf - http://www.DataSheet4U.net/
5 Page 
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Table 5. Characteristics …continued
VDDA(1V8) = 1.8 V; VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 C; RL = 50 ; IO(fs) = 20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in Figure 29; output level = 1 V (p-p).
Symbol
Parameter
Conditions
Test
[1]
Min
Typ Max
Unit
tsu
set-up time
manual tuning mode (see
Figure 16); depends on
LDCLK_DEL[3:0]
0000
C 300
-
0001
C 365
-
0010
C 440
-
0011
C 520
-
0100
C 590
-
0101
C 675
-
0110
C 750
-
0111
C 830
-
1000
C 845
-
1001
C 845
-
1010
C 1000
-
1011
C 1100
-
1100
C 1220
-
1101
1110
C
http://www.DataSheet4U.net/
C
1290
1360
-
-
1111
C 1450
-
thold
hold time
manual tuning mode (see
Figure 15); depends on
LDCLK_DEL[3:0]:
0000
C 790
-
0001
C 870
-
0010
C 950
-
0011
C 1055
-
0100
C 1140
-
0101
C 1230
-
0110
C 1360
-
0111
C 1460
-
1000
C 1900
-
1001
C 2075
-
1010
C 2250
-
1011
C 2400
-
1100
C 2560
-
1101
C 2740
-
1110
C 2900
-
1111
C 3000
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
DAC1617D1G0 3
Preliminary data sheet
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
11 of 78
datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DAC1617D1G0.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DAC1617D1G0 | Dual 16-bit DAC | IDT |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |