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PDF MMA6527KWR2 Data sheet ( Hoja de datos )
| Número de pieza | MMA6527KWR2 | |
| Descripción | Dual-Axis SPI Inertial Sensor | |
| Fabricantes | Motorola Semiconductor Products | |
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Freescale Semiconductor
Data Sheet: Advance Information
Dual-Axis SPI Inertial Sensor
MMA65xx is a SPI-based, dual-axis, medium-g, over-damped lateral acceler-
ometer designed for use in Automotive Airbag systems.
Features
• ±80g, ±105g or ±120g full-scale range, independently specified for each axis
• 3.3V or 5V single supply operation
• SPI-compatible serial interface
• 12-bit digital signed or unsigned SPI data output
• Independent programmable arming functions for each axis
• Twelve low-pass filter options, ranging from 50 Hz to 1000 Hz
• Optional offset cancellation with > 6s averaging period and < 0.25 LSB/s slew
rate
• Pb-Free 16-Pin QFN-6 by 6 Package
Referenced Documents
• AECQ100, Revision G, dated May 14, 2007 (http://www.aecouncil.com/)
Device
MMA6519KWR2
MMA6525KWR2
MMA6527KWR2
ORDERING INFORMATION
X-Axis Range
Y-Axis Range
±80g
±80g
±105g
±105g
±120g
±120g
Shipping
Tape & Reel
Tape & Reel
Tape & Reel
Document Number: MMA65XX
Rev 2, 09/2011
MMA65xx
Bottom View
16 LEAD QFN
6 mm by 6 mm
CASE 2086-01
VCC
VCC
CS
VREG
SCLK
VREGA
MOSI
MISO
C1 C2 C3
MMA65xx
VSSA
VSS
VPP/TEST
ARM_X
ARM_Y
Figure 1. Application Diagram
Table 1. External Component Recommendations
Ref Des
Type
Description
C1
Ceramic
0.1 μF, 10%, 10V Minimum, X7R
C2
Ceramic
1 μF, 10%, 10V Minimum, X7R
C3
Ceramic
1 μF, 10%, 10V Minimum, X7R
Purpose
VCC Power Supply Decoupling
Voltage Regulator Output Capacitor (CVREG)
Voltage Regulator Output Capacitor (CVREGA)
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2011. All rights reserved.
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2.3 Electrical Characteristics - Power Supply and I/O
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified
# Characteristic
Symbol
Min
18 Supply Current
Power Supply Monitor Thresholds (See Figure 9)
19 VCC Under Voltage (Falling)
20 VREG Under Voltage (Falling)
21 VREG Over Voltage (Rising)
22 VREGA Under Voltage (Falling)
23 VREGA Over Voltage (Rising)
Power Supply Monitor Hysteresis
24 VCC Under Voltage
25
26
VREG Under Voltage, VREG Over Voltage
VREGA Under Voltage, VREGA Over Voltage
* IDD
*
*
*
*
*
VCC_UV_f
VREG_UV_f
VREG_OV_r
VREGA_UV_f
VREGA_OV_r
VHYST
VHYST
VHYST
4.0
2.74
2.10
2.65
2.20
2.65
65
20
20
Power Supply RESET Thresholds
(See Figure 6, and Figure 9)
27 VREG Under Voltage RESET (Falling)
28 VREG Under Voltage RESET (Rising)
29 VREG RESET Hysteresis
* VREG_UVR_f
* VREG_UVR_r
VHYST
1.764
1.876
80
Internally Regulated Voltages
30 VREG
31 VREGA
* VREG
* VREGA
2.42
2.42
External Filter Capacitor (CVREG, CVREGA)
32 Value
33 ESR (including interconnect resistance)
CVREG, CVREGA
ESR
700
—
Power Supply Coupling
34 50 kHz ≤ fn ≤ 300 kHz
35 4 MHz ≤ fn ≤ 100 MHz
—
—
Output High Voltage (MISO, PCM_X, PCM_Y)
36 3.15V ≤ (VCC - VSS) ≤ 3.45V (ILoad = -1 mA)
37 4.75V ≤ (VCC - VSS) ≤ 5.25V (ILoad = -1 mA)
* VOH_3
* VOH_5
VCC - 0.2
VCC - 0.4
Output Low Voltage (MISO, PCM_X, PCM_Y)
38 3.15V ≤ (VCC - VSS) ≤ 3.45V (ILoad = 1 mA)
39 4.75V ≤ (VCC - VSS) ≤ 5.25V (ILoad = 1 mA)
* VOL_3
* VOL_5
—
—
Open Drain Output High Voltage (ARM_X, ARM_Y)
40 3.15V ≤ (VCC - VSS) ≤ 3.45V (IARM = -1 mA)
41 4.75V ≤ (VCC - VSS) ≤ 5.25V (IARM = -1 mA)
* VODH_3
* VODH_5
VCC - 0.2
VCC - 0.4
Open Drain Output Pulldown Current (ARM_X, ARM_Y)
42 3.15V ≤ (VCC - VSS) ≤ 3.45V (VARM = 1.5V)
*
43 4.75V ≤ (VCC - VSS) ≤ 5.25V (VARM = 1.5V)
*
IODPD_3
IODPD_5
50
50
Open Drain Output Low Voltage (ARM_X, ARM_Y)
44 3.15V ≤ (VCC - VSS) ≤ 3.45V (IARM = 1 mA)
45 4.75V ≤ (VCC - VSS) ≤ 5.25V (IARM = 1 mA)
* VODH_3
* VODH_5
—
—
Open Drain Output Pullup Current (ARM_X, ARM_Y)
46 3.15V ≤ (VCC - VSS) ≤ 3.45V (VARM = 1.5V)
47 4.75 V ≤ (VCC - VSS) ≤ 5.25V (VARM = 1.5V)
*
*
IODPU_3
IODPU_5
-100
-100
48 Input High Voltage CS, SCLK, MOSI
49 Input Low Voltage CS, SCLK, MOSI
50 Input Voltage Hysteresis CS, SCLK, MOSI
Input Current
51 High (at VIH) (SCLK, MOSI)
52 Low (at VIL) (CS)
* VIH
* VIL
* VI_HYST
* IIH
* IIL
2.0
—
0.125
-70
30
Typ
—
—
—
—
—
—
100
100
100
—
—
—
2.50
2.50
1000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-50
50
Sensor
Freescale Semiconductor
Max Units
8.0 mA (1)
3.02 V (3,6)
2.25 V (3,6)
2.85 V (3,6)
2.35 V (3,6)
2.85 V (3,6)
110 mV (3)
210 mV (3)
150 mV (3)
2.024
2.152
140
V (3,6)
V (3,6)
mV (3)
2.58 V (1,3)
2.58 V (1,3)
1500
400
nF (19)
mΩ (19)
0.004
0.004
LSB/mv (19)
LSB/mv (19)
— V (2,3)
— V (2,3)
0.2 V (2,3)
0.4 V (2,3)
— V (2,3)
— V (2,3)
100 μA (2,3)
100 μA (2,3)
0.2 V (2,3)
0.4 V (2,3)
-50
-50
—
1.0
0.500
-30
70
μA (2,3)
μA (2,3)
V (3,6)
V (3,6)
V (19)
μA (2,3)
μA (2,3)
MMA65xx
5
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3 Functional Description
3.1 Customer Accessible Data Array
A customer accessible data array allows for each device to be customized. The array consists of an OTP factory programma-
ble block and read/write registers for device programmability and status. The OTP and writable register blocks incorporate inde-
pendent CRC circuitry for fault detection (reference Section 3.2). The writable register block includes a locking mechanism to
prevent unintended changes during normal operation. Portions of the array are reserved for factory-programmed trim values. The
customer accessible data is shown in the table below.
Table 3. Customer Accessible Data
Location
Bit Function
Type
Addr Register
7
6
5
4
3
2
1
0
$00 SN0
SN[7]
SN[6]
SN[5]
SN[4]
SN[3]
SN[2]
SN[1]
SN[0]
$01 SN1
SN[15]
SN[14]
SN[13]
SN[12]
SN[11]
SN[10]
SN[9]
SN[8]
$02 SN2
SN[23]
SN[22]
SN[21]
SN[20]
SN[19]
SN[18]
SN[17]
SN[16]
$03 SN3
SN[31]
SN[30]
SN[29]
SN[28]
SN[27]
SN[26]
SN[25]
SN[24]
$04 STDEFL_X
STDEFL_X[7]
STDEFL_X[6]
STDEFL_X[5]
STDEFL_X[4]
STDEFL_X[3]
STDEFL_X[2]
STDEFL_X[1]
STDEFL_X[0]
F
$05 STDEFL_Y
STDEFL_Y[7]
STDEFL_Y[6]
STDEFL_Y[5]
STDEFL_Y[4]
STDEFL_Y[3]
STDEFL_Y[2]
STDEFL_Y[1]
STDEFL_Y[0]
$06 FCTCFG_X
1
0
0
0
0
0
0
1
$07 FCTCFG_Y
1
0
0
0
0
0
0
1
$08 PN
PN[7]
PN[6]
PN[5]
PN[4]
PN[3]
PN[2]
PN[1]
PN[0]
$09 Invalid Address: “Invalid Register Request”
$0A DEVCTL
RES_1
RES_0
OCPHASE[1]
OCPHASE[0]
OFFCFG_EN
Reserved
Reserved
Reserved
$0B DEVCFG
OC
Reserved
ENDINIT
SD
OFMON
A_CFG[2]
A_CFG[1]
A_CFG[0]
$0C DEVCFG_X
ST_X
Reserved
Reserved
Reserved
LPF_X[3]
LPF_X[2]
LPF_X[1]
LPF_X[0]
$0D DEVCFG_Y
ST_Y
Reserved
Reserved
Reserved
LPF_Y[3]
LPF_Y[2]
LPF_Y[1]
LPF_Y[0]
$0E ARMCFGX
$0F ARMCFGY
Reserved
Reserved
Reserved
Reserved
APS_X[1]
APS_Y[1]
APS_X[0]
APS_Y[0]
AWS_XN[1]
AWS_YN[1]
AWS_XN[0]
AWS_YN[0]
AWS_XP[1]
AWS_YP[1]
AWS_XP[0]
AWS_YP[0]
R/W
$10 ARMT_XP
AT_XP[7]
AT_XP[6]
AT_XP[5]
AT_XP[4]
AT_XP[3]
AT_XP[2]
AT_XP[1]
AT_XP[0]
$11 ARMT_YP
AT_YP[7]
AT_YP[6]
AT_YP[5]
AT_YP[4]
AT_YP[3]
AT_YP[2]
AT_YP[1]
AT_YP[0]
$12 ARMT_XN
AT_XN[7]
AT_XN[6]
AT_XN[5]
AT_XN[4]
AT_XN[3]
AT_XN[2]
AT_XN[1]
AT_XN[0]
$13 ARMT_YN
AT_YN[7]
AT_YN[6]
AT_YN[5]
AT_YN[4]
AT_YN[3]
AT_YN[2]
AT_YN[1]
AT_YN[0]
$14 DEVSTAT
UNUSED
IDE
UNUSED
DEVINIT
MISOERR
OFF_Y
OFF_X
DEVRES
$15 COUNT
COUNT[7]
COUNT[6]
COUNT[5]
COUNT[4]
COUNT[3]
COUNT[2]
COUNT[1]
COUNT[0]
$16 OFFCORR_X OFFCORR_X[7] OFFCORR_X[6] OFFCORR_X[5] OFFCORR_X[4] OFFCORR_X[3] OFFCORR_X[2] OFFCORR_X[1] OFFCORR_X[0]
$17 OFF_CORR_Y OFFCORR_Y[7] OFFCORR_Y[6] OFFCORR_Y[5] OFFCORR_Y[4] OFFCORR_Y[3] OFFCORR_Y[2] OFFCORR_Y[1] OFFCORR_Y[0]
R
$1C Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
$1D Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type codes
F: Factory programmed OTP location
R: Read-only register
R/W:
N/A:
Read/write register
Not applicable
Sensor
Freescale Semiconductor
MMA65xx
11
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