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PDF AR6002 Data sheet ( Hoja de datos )
| Número de pieza | AR6002 | |
| Descripción | ROCm Single-Chip MAC/BB/Radio | |
| Fabricantes | Atheros | |
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Data Sheet
PRELIMINARY
April 2008
AR6002 ROCmTM Single-Chip MAC/BB/Radio for 2.4/5 GHz
Embedded WLAN Applications
General Description
are available in Wafer Level Chip Scale Packages
The Atheros AR6002 is the 2nd generation of the
(WLCSP) or Ball Grid Arrays (BGA) packaging .
WLAN ROCm family. Building on the advanced
AR6002 Features
performance and features of the AR6001 family,
the compact size and low power consumption of
this single chip design make it an ideal vehicle
for adding WLAN to hand-held and other
battery-powered consumer electronic devices.
■ All-CMOS IEEE 802.11a/b/g or 802.11b/g
single-chip client
■ Integrated PA, LNA and RF switch
minimizing external component count
Both IEEE 802.11g (2.4 GHz) and 802.11a (5 GHz)
■ Data rates of 1–54 Mbps for 802.11g, 6-54
standards are supported by the AR6002 family.
Mbps for 802.11a
The AR6002 supports both SDIO 1.1 and GSPI
lhost interfaces.
tiaThe AR6002 family includes a highly integrated,
nfront-end module ((Power Amplifier, Low-Noise
eAmplifier and RF switch), enabling low-cost
fiddesigns with minimal external components. The
nRF performance, data throughput, and power
oconsumption further improve upon the
Cperformance of the AR6001 family. Advanced
sarchitecture and protocol techniques save power
roduring sleep, stand-by and active states.
theFast antenna diversity is also supported,
Aallowing optimal antenna selection on a per-
:packet basis. The AR6002 family supports 2, 3
ryand 4 wire Bluetooth coexistence protocols with
aadvanced algorithms for predicting channel
inusage by the co-located Bluetooth transceiver.
limThe AR6002 family provides multiple peripheral
reinterfaces including UART, SPI, I2C and 18 GPIO
Ppins. All internal clocks are generated from a
■ Advanced power management to minimize
standby, sleep and active power
■ Host interface support for SDIO and GSPI
■ Security support for WPS, WPA2, WPA,
WAPI and protected management frames
■ Support for 2.4 and 5 GHz operation in all
available bands in all regulatory domains
■ Full 802.11e QoS support including WMM
and U-APSD
■ Standard 2, 3 and 4 wire Bluetooth
coexistence handshake support
■ IEEE 1149.1, JTAG, test access port and
boundary scan
■ 18 fully-programmable GPIO pins
■ 16550-compliant UART
■ SPI or I2C for EEPROM support
■ Internally generated low-frequency oscillator
for low-power sleep
single external crystal/oscillator. A variety of
reference clocks are supported which include
19.2, 24, 26, 38.4, 40 and 52 MHz. AR6002 chips
■ Available in 7 x 7 mm BGA package with 0.5
mm pitch or WLCSP package with 0.4 mm
pitch
HOST
SDIO or GSPI
SDIO
GSPI
Console
EEPROM
LED
Test, ICE
UART
SPI/I2C
GPIO
JTAG
PA
Mailbox A 802.11a/g 802.11a/g 802.11a/g
DMA
H
MAC
BB
Radio
LNA1
B
Bridge
AR6002
I
N
T
E
R
N
A
L
B
U
S
Memory
Controller
RAM
ROM
i-port
d-port
Power, Clock
Management
LNA2
Xtensa
CPU
LF CLK
REF CLK
AR6002 System Block Diagram
LNA2 Input
32 KHz OSC
(optional)
OSC/XTAL
© 2000-2008 by Atheros Communications, Inc. All rights reserved. Atheros™, ROCm™, 5-UP™, Driving the Wireless Future™, Atheros Driven™, Atheros
Turbo Mode™, and the Air is Cleaner at 5-GHz™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of
Atheros Communications, Inc. All other trademarks are the property of their respective holders.
Subject to change without notice.
PRELIMINARY: ATHEROS CONFIDENTIAL
•1
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
1. Functional Description
1.1 Overview
Any one of these interfaces can request access
The AR6002 is a single chip 802.11 (a, b, g)
device based on the cutting edge technology.
The AR6002 has large internal RAM which
to the ROM or RAM modules within the VMC.
The VMC contains arbiters to serve these three
interfaces on a first-come-first-serve basis.
precludes the need for external memory. It
contains a dual-band radio, a MAC, a CPU,
1.4 AHB and APB Blocks
power management functions, and other
The AHB block acts as an arbiter. It has AHB
functions. Its internal logic and boot code are
interfaces from three Masters:
designed to detect the presence of an external
host and to automatically begin
■ MAC,
communicating with that host. The supported
■ MBOX (from the Host), and
Host interfaces are SDIO and GSPI (Generic
■ CPU.
SPI). See the AR6002 block diagram on page 1.
See below for more on the MBOX and MAC.
The XTENSA CPU communicates directly with
Depending upon the address, the AHB data
the RAM and ROM modules within the device
lwithout any caching. Boot code in the ROM
tiafirst detects the presence of an external host. It
then begins communicating with this host. The
enhost then downloads additional code into the
fidRAM which the XTENSA CPU can later
execute.
onThe AR6002 supports a total of 18 GPIOs. Some
Cof these GPIOs are shared with the UART
sinterface as well as the SI block. The SI block
rosupports both I2C as well as SPI interfaces and
thecan be used to communicate with external
serial devices such as EEPROMs or
Aprogrammable oscillators.
ary:1.2 XTENSA CPU
inAt the heart of the chip is the XTENSA CPU.
limThis CPU has four interfaces:
re■ The Code RAM/ROM interface (iBus),
going to the Virtual Memory Controller
P(VMC).
request can go into one of the two slaves: APB
block or the VMC. Data requests to the VMC
are generally high-speed memory requests,
while requests to the APB block are primarily
meant for register access.
The APB block acts as a decoder. It is meant
only for access to programmable registers
within the AR6002’s main blocks. Depending
upon the address, the APB request can go to
one of the eight places listed below:
■ RF Interface (APB serial block)
■ VMC
■ SI/SPI
■ MBOX
■ GPIO
■ UART
■ Real Time Clock (RTC), or
■ MAC/BB
■ The Data RAM Interface (dBus), going to
the VMC
■ The AHB interface which has been
translated from the CPU's internal XTENSA
Local Memory Interface (XLMI) bus. This is
used mainly for register accesses.
The AR6002 RF module has a long-shift
interface which allows the CPU to directly
control its registers via APB access. Hence the
APB block converts 32-bit APB reads and
writes by the CPU into serial transfers to the RF
module.
■ JTAG interface for debugging
1.5 Master SI/SPI Control
1.3 Virtual Memory Controller (VMC)
The VMC contains 80 kBytes of ROM and 184
kBytes of RAM. It has three interfaces:
■ iBus,
■ dBus, and
■ AHB interface.
The AR6002 has a master serial interface (SI)
that can operate in two, three, or four-wire bus
configurations to control EEPROMs or other
I2C/SPI devices. Multiple I2C devices with
different device addresses are supported by
sharing the two-wire bus. Multiple SPI devices
are supported by sharing the clock and data
signals and using separate software-controlled
GPIO pins as chip selects.
Atheros Communications, Inc.
PRELIMINARY: ATHEROS CONFIDENTIAL
AR6002 MAC/BB/Radio for Embedded WLAN Applications • 5
April 2008 • 5
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
However, the external clock source need not
run at 32 KHz. It can be running at any similar
low frequency. The TSF and other low
frequency timers need to be programmed to
match this frequency.
In addition to providing the low-frequency
sleep clock for the AR6002, the 2 MHz ring
oscillator also runs the state machines and
counters inside the AR6002's Power Control
Module (PCM). The PCM controls all power
and isolation control signals for the entire chip.
AR6002 information, including SDIO Common
I/O Area (CIA), when the AR6002 is in SLEEP
state.
1.13.4 Antenna Switching
For designs that use external front-end
components, the AR6002 provides the ability to
control those components and the internal
LNA with the antenna switch table. The switch
table (see Table 1-2) contains 10 entries, each 5
bits wide, and is indexed by:
1.13.3 Interface Clock
■ The antenna selected by the MAC
In addition to the clocking mentioned above,
there is another clock source for the AR6002.
■ The state of the transceiver (idle, receive, or
transmit)
This clock is referred to as the host clock (either
SDIO or GSPI). This clock is completely
lindependent from those mentioned above and
tiais driven by the external host to communicate
nwith the AR6002
fideThis clock drives the interface logic as well as a
few registers which can be accessed by the
nhost. This allows this host to probe some
■ Controls for Rx attenuation
When fast-receive antenna diversity is enabled,
the baseband will temporarily override the
antenna selected by the MAC once a packet has
been detected.
CoNOTE: Refer to AR6002 ART Reference Guide for more details on switching.
therosTable 1-2. Switch Table
: AChip
ryState
inaIdle
Bluetooth
limActive
PreTx
Ant
Select
—
—
Rx Atten
—
—
Register Name
BB_ANTENNA_CONTROL
BB_ANTENNA_CONTROL
1—
BB_SWITCH_TABLE1
Rx 1 No
Rx 1 Yes
Rx 1 Yes
Tx
2—
BB_SWITCH_TABLE2
Rx 2 No
Rx 2 Yes
Rx 2 Yes
Atheros Communications, Inc.
PRELIMINARY: ATHEROS CONFIDENTIAL
AR6002 MAC/BB/Radio for Embedded WLAN Applications • 11
April 2008 • 11
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 56 Páginas | |
| PDF Descargar | [ Datasheet AR6002.PDF ] | |
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