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PDF CYF1036V Data sheet ( Hoja de datos )
| Número de pieza | CYF1036V | |
| Descripción | 18/36/72-Mbit Programmable 2-Queue FIFOs | |
| Fabricantes | Cypress Semiconductor | |
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CYF1018V, CYF1036V
CYF1072V
18/36/72-Mbit Programmable
2-Queue FIFOs
18/36/72-Mbit Programmable 2-Queue FIFOs
Features
■ Memory organization
❐ Industry’s largest first in first out (FIFO) memory densities:
18-Mbit, 36-Mbit, 72-Mbit
❐ Selectable memory organization: × 9, × 12, × 16, × 18, × 20,
× 24, × 32, × 36
■ Up to 100-MHz clock operation
■ Unidirectional operation
■ Independent read and write ports
❐ Supports simultaneous read and write operations
❐ Reads and writes operate on independent clocks upto a
maximum clock ratio of 2, enabling data buffering across
clock domains
❐ Supports multiple I/O voltage standard: Low voltage
complementary metal oxide semiconductor (LVCMOS) 3.3 V
and 1.8 V voltage standards.
■ output enable control for read skip operations
■ User configured two-Queue operating mode
■ Mark and retransmit: resets read pointer to user marked
position
■ Empty and full status flags
■ Flow-through mailbox register to send data from input to output
port, bypassing the FIFO sequence
■ Configure programmable flags and registers through serial or
parallel modes
■ Separate serial clock (SCLK) input for serial programming
■ Master reset to clear entire FIFO
■ Joint test action group (JTAG) port provided for boundary scan
function
■ Industrial temperature range: –40 °C to +85 °C
Functional Description
The Cypress programmable FIFO family offers the industry’s
highest-density programmable FIFO memory device. It has
independent read and write ports, which can be clocked up to
100 MHz. User can configure input and output bus sizes. The
maximum bus size of 36 bits enables a maximum data
throughput of 3.6 Gbps. The read and write ports can support
multiple I/O voltage standards. The user-programmable
registers enable user to configure the device operation as
desired. The device also offers a simple and easy-to-use
interface to reduce implementation and debugging efforts,
improve time-to-market, and reduce engineering costs. This
makes it an ideal memory choice for a wide range of applications
including multiprocessor interfaces, video and image
processing, networking and telecommunications, high-speed
data acquisition, or any system that needs buffering at very high
speeds across different domains.
As implied by the name, the functionality of the FIFO is such that
the data is read out of the read port in the same sequence in
which it was written into the write port. The data is sequentially
written into the FIFO from the write port. If the writes and inputs
are enabled, the data on the write port gets written into the device
at the rising edge of the write clock. Enabling the reads and
outputs fetches data on the read port at every rising edge of the
read clock. Both reads and writes can occur simultaneously at
different speeds provided the ratio of read to write clock is
between 0.5 and 2. Appropriate flags are set whenever the FIFO
is empty or full.
The device also supports two-Queue operation, mark and
retransmit of data, and a flow-through mailbox register.
All product features and specs are common to all densities
(CYF1072V, CYF1036V, and CYF1018V) unless otherwise
specified. All descriptions are given assuming the device is
CYF1072V operated in × 36 mode. They hold good for other
densities (CYF1036V, and CYF1018V) and all port sizes × 9,
×12, × 16, × 18, × 20, × 24 and × 32 unless otherwise specified.
the only difference will be in the input and output bus width.
Table 1 on page 8 shows the part of bus with valid data from
D[35:0] and Q[35:0] in × 9, × 12, × 16, × 18, × 20, × 24, × 32 and
× 36 modes.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4NUu.nmebt er: 001-68321 Rev. **
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 12, 2011
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CYF1018V, CYF1036V
CYF1072V
Pin Definitions
Pin Name
D[35:0]
Q[35:0]
WEN
REN
OE
WCLK
RCLK
DVal0
DVal1
EF
FF
LD
RT
MRS
SPI_SCLK
SPI_SI
SPI_SEN
MARK
MB
WQSEL0
RQSEL0
TCK
TRST
TMS
TDI
TDO
PORTSZ [2:0]
VCC1
VCC2
I/O
Input
Output
Input
Input
Input
Input
Input
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Power
Supply
Power
Supply
Pin Description
Data inputs: Data inputs for a 36-bit bus.
Data outputs: Data outputs for a 36-bit bus.
Write enable: WEN enables WCLK to write data into the FIFO memory and configuration registers.
Read enable: REN enables RCLK to read data from the FIFO memory and configuration registers.
Output enable: When OE is LOW, FIFO data outputs are enabled; when OE is HIGH, the FIFO’s outputs
are in High Z (high impedance) state.
Write clock: When enabled by WEN, the rising edge of WCLK writes data into the FIFO if LD is high and
into the configuration registers if LD is low.
Read clock: When enabled by REN, the rising edge of RCLK reads data from the FIFO memory if LD is
high and from the configuration registers if LD is low.
Data valid for Queue-0 : Active low signal indicating valid data read for Queue-0 from Q[35:0].
Data valid for Queue-1 : Active low signal indicating valid data read for Queue-1 from Q[35:0].
Empty flag: When EF is LOW, the Queue is empty. EF is synchronized to RCLK.
Full flag: When FF is LOW, the Queue is full. FF is synchronized to WCLK.
Load: When LD is LOW, D[7:0] (Q[7:0]) are written (read) into (from) the configuration registers. When
LD is HIGH, D[35:0] (Q[35:0]) are written (read) into (from) the FIFO.
Retransmit: A HIGH pulse on RT resets the internal read pointer to a physical location of the FIFO which
is marked by the user (using MARK pin). With every valid read cycle after retransmit, previously accessed
data is read and the read pointer is incremented until it is equal to the write pointer.
Master reset: MRS initializes the read and write pointers to zero and sets the output register to all zeroes.
During Master Reset, the configuration registers are all set to default values and flags are reset.
Serial clock: A rising edge on SPI_SCLK clocks the serial data present on the SPI_SI input into the offset
registers if SPI_SEN is enabled.
Serial input: Serial input when SPI_SEN is enabled.
Serial enable: Enables serial loading of programmable flag offsets and configuration registers.
Mark for retransmit: When this pin is asserted the current location of the read pointer is marked. Any
subsequent retransmit operation resets the read pointer to this position.
Mailbox: When asserted the reads and writes happen to flow-through mailbox register.
Write Queue select: select Queue-0 when low and Queue-1 when high.
Read Queue select: select Queue-0 when low and Queue-1 when high.
Test clock (TCK) pin for JTAG.
Reset pin for JTAG.
Test mode select (TMS) pin for JTAG.
Test data in (TDI) pin for JTAG.
Test data out (TDO) for JTAG.
Port word size select: Port word width select pins (common for read and write ports).
Core voltage supply 1: 1.8 V supply voltage
Core voltage supply 2: 1.5 V supply voltage
Document Number: 001-68321 Rev. **
Page 5 of 28
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5 Page 
CYF1018V, CYF1036V
CYF1072V
Figure 3. Using Two CYF1072V for Width Expansion
DATAIN (D) 72 36
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
CYF1072V
FF EF
FF
36
36
CYF1072V
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE(OE)
EF
FF EF
36 DATA OUT (Q) 72
Memory Organization for Different Port Sizes
The 72-Mbit memory has different organization for different port
sizes. Table 6 shows the depth of the FIFO for all port sizes.
Note that for all port sizes, four to eight locations are not available
for writing the data and are used to safeguard against false
synchronization of empty and full flags.
Table 6. Word Size Selection
PORTSZ[2:0] Word Size FIFO Depth Memory Size
000
×9
8 Meg
72 Mbit
001
× 12
4 Meg
48 Mbit
010
× 16
4 Meg
64 Mbit
011
× 18
4 Meg
72 Mbit
100
× 20
2 Meg
40 Mbit
101
× 24
2 Meg
48 Mbit
110
× 32
2 Meg
64 Mbit
111
× 36
2 Meg
72 Mbit
The memory size mentioned is when the device is configured in
single-Queue mode.
Read/Write Clock Requirements
The read and write clocks must satisfy the following
requirements:
■ Both read (RCLK) and write (WCLK) clocks should be
free-running.
■ The clock frequency for both clocks should be between the
minimum and maximum range given in Switching
Characteristics on page 15.
■ The ratio of RCLK to WCLK must be in the range of 0.5 to 2.
The device uses internal PLL to achieve high performance.
Whenever there is change in the frequency of the clock, the
device takes tPLL time to synchronize with the input clock. (see
Switching Characteristics on page 15). The PLL requires
re-synchronization when there is change in the frequency of
either WCLK or RCLK or when master reset is asserted.
For proper FIFO operation, the device must determine which of
the input clocks – RCLK or WCLK – is faster. This is evaluated
by using counters after the MRS cycle. The device uses two
10-bit counters inside (one running on RCLK and other on
WCLK), which count 1,024 cycles of read and write clock after
MRS. The clock of the counter which reaches its terminal count
first is used as master clock inside the FIFO.
When there is change in the relative frequency of RCLK and
WCLK during normal operation of FIFO, user can specify it by
using “Fast CLK bit” in the configuration register (0xA).
“1” - indicates freq (WCLK) > freq (RCLK)
“0” - indicates freq (WCLK) < freq (RCLK)
The result of counter evaluated frequency is available in this
register bit. User can override the counter evaluated frequency
for faster clock by changing this bit.
Whenever there is a change in this bit value, user must wait tPLL
time before issuing the next read or write to FIFO.
JTAG operation
CYF1072V has two devices connected internally in a JTAG chain
as shown in Figure 4 on page 12.
Document Number: 001-68321 Rev. **
Page 11 of 28
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| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet CYF1036V.PDF ] | |
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