PDF CY7C1911BV18 Data sheet ( Hoja de datos )

Número de pieza	CY7C1911BV18
Descripción	(CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
Fabricantes	Cypress Semiconductor
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CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth • 4-Word Burst for reducing address bus frequency • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 600 MHz) at 300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • Available in x 8, x 9, x 18, and x 36 configurations • Full data coherency providing most current data • Core VDD = 1.8 (±0.1V); I/O VDDQ = 1.4V to VDD • Available in 165-ball FBGA package (13 x 15 x 1.4 mm) • Offered in both lead-free and non-lead free packages • Variable drive HSTL output buffers • JTAG 1149.1 compatible test access port • Delay Lock Loop (DLL) for accurate data placement Configurations CY7C1311BV18 – 2M x 8 CY7C1911BV18 – 2M x 9 CY7C1313BV18 – 1M x 18 CY7C1315BV18 – 512K x 36 The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1311BV18) or 9-bit words (CY7C1911BV18) or 18-bit words (CY7C1313BV18) or 36-bit words (CY7C1315BV18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simpli- fying system design by eliminating bus “turn-arounds”. Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Selection Guide Maximum Operating Frequency Maximum Operating Current 300 MHz 300 550 278 MHz 278 530 250 MHz 250 500 200 MHz 200 450 167 MHz 167 400 Unit MHz mA Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 38-05620 Rev. C Revised June 27, 2006 www.DataSheet.in [+] Feedback 1 page CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 Pin Configurations (continued) 165-ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1313BV18 (1M x 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/144M NC/36M WPS BWS1 K NC/288M RPS A NC/72M CQ B NC Q9 D9 A NC K BWS0 A NC NC Q8 C NC NC D10 VSS A NC A VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS A A A VSS NC NC D1 P NC NC Q17 A A C A A NC D0 Q0 R TDO TCK A A ACAA A TMS TDI CY7C1315BV18 (512K x 36) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/288M NC/72M WPS BWS2 K BWS1 RPS NC/36M NC/144M CQ B Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 C D27 Q28 D19 VSS A NC A VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2 N D34 D26 Q25 VSS A A A VSS Q10 D9 D1 P Q35 D35 Q26 A A C A A Q9 D0 Q0 R TDO TCK A A A CAA A TMS TDI Document Number: 38-05620 Rev. C www.DataSheet.in Page 5 of 28 [+] Feedback 5 Page CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 Write Cycle Descriptions(CY7C1315BV18)[2, 10] BWS0 BWS1 BWS2 BWS3 K L L L L L–H LLLL– L H H H L–H L HHH – H L H H L–H H L HH – H H L H L–H HH L H – H H H L L–H HHHL – H H H H L–H HHHH – K Comments – During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. L–H During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. – During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. L–H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. – During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. L–H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. – During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. L–H During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. L–H During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. – No data is written into the device during this portion of a write operation. L–H No data is written into the device during this portion of a write operation. Write Cycle Descriptions (CY7C1911BV18)[2, 10] BWS0 L L H H KK L–H – During the Data portion of a Write sequence, the single byte (D[8:0]) is written into the device. – L–H During the Data portion of a Write sequence, the single byte (D[8:0]) is written into the device. L–H – No data is written into the device during this portion of a write operation. – L–H No data is written into the device during this portion of a write operation. Document Number: 38-05620 Rev. *C www.DataSheet.in Page 11 of 28 [+] Feedback 11 Page

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