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PDF LTC2392-16 Data sheet ( Hoja de datos )
| Número de pieza | LTC2392-16 | |
| Descripción | 500ksps SAR ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Features
n 500ksps Throughput Rate
n ±2LSB INL (Max)
n Guaranteed 16-Bit No Missing Codes
n 94dB SNR (Typ) at fIN = 20kHz
n Guaranteed Operation to 125°C
n Single 5V Supply
n 1.8V to 5V I/O Voltages
n 110mW Power Dissipation
n ±4.096V Differential Input Range
n Internal Reference (20ppm/°C Max)
n No Pipeline Delay, No Cycle Latency
n Parallel and Serial Interface
n Internal Conversion Clock
n 48-Pin 7mm × 7mm LQFP and QFN Packages
Applications
n Medical Imaging
n High Speed Data Acquisition
n Digital Signal Processing
n Industrial Process Control
n Instrumentation
n ATE
LTC2392-16
16-Bit, 500ksps SAR ADC
with 94dB SNR
Description
The LTC®2392-16 is a low noise, high speed 16-bit suc-
cessive approximation register (SAR) ADC. Operating
from a single 5V supply, the LTC2392-16 supports a large
±4.096V fully differential input range, making it ideal for
high performance applications which require maximum
dynamic range. The LTC2392-16 achieves ±2LSB INL max,
no missing codes at 16-bits and 94dB SNR (typ).
The LTC2392-16 includes a precision internal reference
with a guaranteed 0.5% initial accuracy and a ±20ppm/°C
(max) temperature coefficient. Fast 500ksps throughput
with no cycle latency in both parallel and serial interface
modes makes the LTC2392-16 ideally suited for a wide va-
riety of high speed applications. An internal oscillator sets
the conversion time, easing external timing considerations.
The LTC2392-16 dissipates only 110mW at 500ksps, while
both nap and sleep power-down modes are provided to
further reduce power during inactive periods.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
typical application
ANALOG INPUT
0V TO 4.096V
249Ω
LT6350
2200pF
249Ω
SINGLE-ENDED-
TO-DIFFERENTIAL
DRIVER
5V 5V 1.8V TO 5V
10µF
0.1µF
10µF
0.1µF
4.7µF
AVP
IN+
DVP OVP PARALLEL
OR
SERIAL
16 BIT
INTERFACE
LTC2392-16
SER/PAR
BYTESWAP
IN–
OB/2C
CS
RD
VCM REFIN REFOUT CNVST PD RESET GND OGND
BUSY
239216 TA01
10µF
1µF SAMPLE CLOCK
www.DataSheet.in
16k Point FFT fS = 500ksps,
fIN = 20kHz
0
SNR = 94dB
–20 THD –103dB
–40
SINAD = 93.5dB
SFDR = 104dB
–60
–80
–100
–120
–140
–160
–180
0
50 100 150 200
FREQUENCY (kHz)
250
239216 G08
239216f
1 page  
LTC2392-16
timing characteristics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
fSMPL
tCONV
tACQ
t4
t5
t6
Sampling Frequency
Conversion Time
Acquisition Time
CNVST Low Time
CNVST High Time
CNVST↓ to BUSY Delay
CL = 15pF
l
l
l
l 20
l 250
l
500 ksps
1300 ns
685 ns
ns
ns
15 ns
t7 RESET Pulse Width
t8 SCLK Period
t9 SCLK High Time
t10 SCLK Low Time
tr , tf SCLK Rise and Fall Times
t11 SDIN Setup Time
t12 SDIN Hold Time
t13 SDOUT Delay After SCLK↑
(Note 9)
(Note 10)
CL = 15pF
l5
l 12.5
l4
l4
l2
l1
l2
ns
ns
ns
ns
1 µs
ns
ns
8 ns
t14 SDOUT Delay After CS↓
t15 CS↓ to SCLK Setup Time
l
l 20
8 ns
ns
t16 Data Valid to BUSY↓
t17 Data Access Time after RD↓ or BYTESWAP↑
l1
l 10
ns
ns
t18 Bus Relinquish Time
l 10 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above
AVP, DVP or OVP, they will be clamped by internal diodes. This product can
handle input currents up to 100mA below ground or above AVP, DVP or
OVP without latchup.
Note 4: AVP = DVP = OVP = 5V, fSMPL = 500ksps, external reference equal
to 4.096V unless otherwise noted.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111. Bipolar full-scale error is the worst-case of –FS or +FS
untrimmed deviation from ideal first and last code transitions and includes
the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±4.096V input
with a 4.096V reference voltage.
Note 9: t13 of 8ns maximum allows a shift clock frequency up to
2 • (t13 + tSETUP) for falling edge capture with 50% duty cycle and up to
80MHz for rising capture. tSETUP is the set-up time of the receiving logic.
Note 10: Guaranteed by design.
Note 11: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
4V
tDELAY
4V
0.5V
0.5V
tDELAY
4V
0.5V
50%
tWIDTH
50%
Figure 1. Voltage Levels for Timing Specifications
239216 F01
www.DataSheet.in
239216f
5 Page 
LTC2392-16
Applications Information
OVERVIEW
The LTC2392-16 is a low noise, high speed 16-bit suc-
cessive approximation register (SAR) ADC. Operating
from a single 5V supply, the LTC2392-16 supports a
large ±4.096V fully differential input range, making it ideal
for high performance applications which require a wide
dynamic range. The LTC2392-16 achieves ±2LSB INL max,
no missing codes at 16 bits and 94dB SNR (typ).
The LTC2392-16 includes a precision internal reference with
a guaranteed 0.5% initial accuracy and a ±20ppm/°C (max)
temperature coefficient. Fast 500ksps throughput with no
cycle latency in both parallel and serial interface modes
makes the LTC2392-16 ideally suited for a wide variety
of high speed applications. An internal oscillator sets the
conversion time, easing external timing considerations.
The LTC2392-16 dissipates only 110mW at 500ksps, while
both nap and sleep power-down modes are provided to
further reduce power during inactive periods.
CONVERTER OPERATION
The LTC2392-16 operates in two phases. During the ac-
quisition phase, the charge redistribution capacitor D/A
converter (CDAC) is connected to the IN+ and IN– pins
to sample the differential analog input voltage. A falling
edge on the CNVST pin initiates a conversion. During the
conversion phase, the 16-bit CDAC is sequenced through a
successive approximation algorithm, effectively comparing
the sampled input with binary-weighted fractions of the
reference voltage (e.g., VREF/2, VREF/4 … VREF/65536)
using the differential comparator. At the end of conversion,
the CDAC output approximates the sampled analog input.
The ADC control logic then prepares the 16-bit digital
output code for parallel or serial transfer.
TRANSFER FUNCTION
The
into
LTC2392-16 digitizes the full-scale voltage
216 levels, resulting in an LSB size of 125µV
of 2 •
when
VREF
VREF
= 4.096V. The ideal transfer function for two’s complement
is shown in Figure 2. The OB/2C pin selects either offset
binary or two’s complement format.
011...111
011...110
000...001
000...000
111...111
111...110
BIPOLAR
ZERO
100...001
100...000
FSR = +FS – –FS
1LSB = FSR/65536
–FSR/2
–1 0V 1
LSB LSB
INPUT VOLTAGE (V)
FSR/2 – 1LSB
239216 F02
Figure 2. LTC2392-16 Two’s Complement Transfer Function
ANALOG INPUT
The analog inputs of the LTC2392-16 are fully differential
in order to maximize the signal swing that can be digitized.
The analog inputs can be modeled by the equivalent circuit
shown in Figure 3. The diodes at the input provide ESD pro-
tection. The analog inputs should not exceed the supply or
go below ground. In the acquisition phase, each input sees
approximately 40pF (CIN) from the sampling CDAC in series
with 50Ω (RIN) from the on-resistance of the sampling
switch. Any unwanted signal that is common to both
inputs will be reduced by the common mode rejection of
the ADC. The inputs draw only one small current spike
while charging the CIN capacitors during acquisition.
During conversion, the analog inputs draw only a small
leakage current.
AVP
IN+
RIN CIN
AVP
IN–
RIN CIN
BIAS
VOLTAGE
239216 F03
Figure 3. The Equivalent Circuit for the
Differential Analog Input of the LTC2392-16
www.DataSheet.in
239216f
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| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC2392-16.PDF ] | |
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