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PDF LTC2382-16 Data sheet ( Hoja de datos )
| Número de pieza | LTC2382-16 | |
| Descripción | Low Power SAR ADC | |
| Fabricantes | Linear Technology | |
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LTC2382-16
16-Bit, 500ksps, Low Power
SAR ADC with Serial Interface
FEATURES
n 500ksps Throughput Rate
n ±2LSB INL (Max)
n Guaranteed 16-Bit No Missing Codes
n Low Power: 6.5mW at 500ksps, 13μW at 1ksps
n 92dB SNR (typ) at fIN = 20kHz
n Extended Acquisition Time of 1.25μs Allows Use of
Lower Power Drivers
n Guaranteed Operation to 125°C
n 2.5V Supply
n Fully Differential Input Range ±2.5V
n External 2.5V Reference Input
n No Pipeline Delay, No Cycle Latency
n 1.8V to 5V I/O Voltages
n SPI-Compatible Serial I/O with Daisy-Chain Mode
n Internal Conversion Clock
n 16-pin MSOP and 4mm × 3mm DFN Packages
APPLICATIONS
n Medical Imaging
n High Speed Data Acquisition
n Portable or Compact Instrumentation
n Industrial Process Control
n Low Power Battery-Operated Instrumentation
n ATE
DESCRIPTION
The LTC®2382-16 is a low noise, low power, high speed
16-bit successive approximation register (SAR) ADC.
Operating from a 2.5V supply, the LTC2382-16 has a
±2.5V fully differential input range. The LTC2382-16
consumes only 6.5mW and achieves ±2LSB INL max, no
missing codes at 16-bits and 92dB SNR.
The LTC2382-16 has a high speed SPI-compatible serial
interface that supports 1.8V, 2.5V, 3.3V and 5V logic
while also featuring a daisychain mode. The fast 500ksps
throughput with no cycle latency makes the LTC2382-16
ideally suited for a wide variety of high speed applica-
tions. An internal oscillator sets the conversion time,
easing external timing considerations. The LTC2382-16
automatically powers down between conversions, lead-
ing to reduced power dissipation that scales with the
sampling rate.
The LTC2382-16 features a proprietary sampling
architecture that enables the ADC to begin acquiring the
next sample during the current conversion. The resulting
extended acquisition time of 1.25μs allows the use of
extremely low power ADC drivers.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
ANALOG INPUT
0V TO 2.5V
50Ω
LT6350
50Ω
SINGLE-ENDED-
TO-DIFFERENTIAL
DRIVER
2.5V 1.8V TO 5V
10μF
0.1μF
100Ω
3300pF
100Ω
IN+ VDD
OVDD
LTC2382-16
IN–
REF
2.5V
GND
CHAIN
RDL/SDI
SDO
SCK
BUSY
CNV
238216 TA01
47μF
(X5R, 0805 SIZE)
SAMPLE CLOCK
www.DataSheet.in
32k Point FFT fS = 500ksps, fIN = 20kHz
0
SNR = 92.2dB
–20 THD = –106dB
SINAD = 92dB
–40 SFDR = 107dB
–60
–80
–100
–120
–140
–160
–180
0
50 100 150 200
FREQUENCY (kHz)
250
238216 TA02a
238216f
1
1 page  
LTC2382-16
ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP
MAX UNITS
tSCK
tSCKH
tSCKL
tSSDISCK
tHSDISCK
tSCKCH
tDSDO
tHSDO
tDSDOBUSYL
tEN
tDIS
tSSCKRDL
tHSCKRDL
SCK Period
SCK High Time
SCK Low Time
SDI Setup Time From SCK ↑
SDI Hold Time From SCK ↑
SCK Period in Chain Mode
SDO Data Valid Delay from SCK ↑
SDO Data Remains Valid Delay from SCK ↑
SDO Data Valid Delay from BUSY ↓
Bus Enable Time After RDL ↓
Bus Relinquish Time After RDL ↑
SCK Setup Time from RDL/SDI ↓
SCK Hold Time from RDL/SDI ↓
(Notes 11, 12)
(Note 11)
(Note 11)
tSCKCH = tSSDISCK + tDSDO (Note 11)
CL = 20pF (Note 11)
CL = 20pF (Note 10)
CL = 20pF (Note 10)
(Note 11)
(Note 11)
(Note 10)
(Note 10)
l 10
l4
l4
l4
l1
l 13.5
l
l1
l
l
l
l1
l 16
ns
ns
ns
ns
ns
ns
9.5 ns
ns
5 ns
16 ns
13 ns
ns
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF or
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latch-up.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 2.5V, fSMPL = 500kHz.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero-scale error is the offset voltage measured from
–0.5LSB when the output code flickers between 0000 0000 0000 0000
and 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of
–FS or +FS untrimmed deviation from ideal first and last code transitions
and includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±2.5V input with
a 2.5V reference voltage.
Note 9: fSMPL = 500kHz, IREF varies proportionately with sample rate.
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 12: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising capture.
0.8*OVDD
tDELAY
0.8*OVDD
0.2*OVDD
0.2*OVDD
tDELAY
0.8*OVDD
0.2*OVDD
tWIDTH
50% 50%
Figure 1. Voltage Levels for Timing Specifications
238216 F01
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238216f
5
5 Page 
LTC2382-16
APPLICATIONS INFORMATION
Single-to-Differential Conversion
For single-ended input signals, a single-ended to differential
conversion circuit must be used to produce a differential
signal at the inputs of the LTC2382-16. The LT6350 ADC
driver is recommended for performing single-ended-to-
differential conversions.The LT6350 is flexible and may
be configured to convert single-ended signals of various
amplitudes to the ±2.5V differential input range of the
LTC2382-16. The LT6350 is also available in H-grade to
complement the extended temperature operation of the
LTC2382-16 up to 125°C.
Figure 5 shows the LT6350 being used to convert a 0V
to 2.5V single-ended input signal. In this case, the first
amplifier is configured as a unity gain buffer and the single-
ended input signal directly drives the high-impedance
input of the amplifier. As shown in the FFT of Figure 5a,
the LT6350 drives the LTC2382-16 to full datasheet
performance without degrading the SNR or THD.
LT6350
0V to 2.5V
8+
1–
RINT
RINT
4 OUT1
–
2+
5 OUT2
+– VCM = VREF/2
0V to
2.5V
2.5V to
0V
238216 F05
Figure 5. LT6350 Converting a 0V-2.5V Single-Ended Signal
to a ±2.5V Differential Input Signal
The LT6350 can also be used to buffer and convert
single-ended signals larger than the input range of the
LTC2382-16 in order to maximize the signal swing that
can be digitized. Figure 6 shows the LT6350 converting a
0V-5V single-ended input signal to the ±2.5V differential
input range of the LTC2382-16. In this case, the first
amplifier in the LT6350 is configured as an inverting
amplifier stage, which acts to attenuate the input signal
down to the 0V-2.5V input range of the LTC2382-16. In the
inverting amplifier configuration, the single-ended input
signal source no longer directly drives a high impedance
input of the first amplifier. The input impedance is instead
set by resistor RIN. RIN must be chosen carefully based on
the source impedance of the signal source. Higher values
of RIN tend to degrade both the noise and distortion of
the LT6350 and LTC2382-16 as a system. R1, R2 and R3
must be selected in relation to RIN to achieve the desired
attenuation and to maintain a balanced input impedance
in the first amplifier. Table 1 shows the resulting SNR
and THD for several values of RIN, R1, R2 and R3 in this
configuration. Figure 6a shows the resulting FFT when
using the LT6350 as shown in Figure 6.
The LT6350 can also be used to buffer and convert large,
true bipolar signals which swing below ground to the ±2.5V
differential input range of the LTC2382-16. Figure 7 shows
the LT6350 being used to convert a ±10V true bipolar signal
for use by the LTC2382-16. The input impedance is again
set by resistor RIN. Table 2 shows the resulting SNR and
THD for several values of RIN. Figure 7a shows the resulting
FFT when using the LT6350 as shown in Figure 7.
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
0
SNR = 92.2dB
THD = –106dB
SINAD = 92dB
SFDR = 107dB
50 100 150 200
FREQUENCY (kHz)
250
238216 F05a
Figure 5a.32k Point FFT Plot for Circuit Shown in Figure 5
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238216f
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| PDF Descargar | [ Datasheet LTC2382-16.PDF ] | |
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