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PDF STM8L101G2 Data sheet ( Hoja de datos )
| Número de pieza | STM8L101G2 | |
| Descripción | STM8L EnergyLite 8-bit MCUs 8-bit ultralow power microcontroller | |
| Fabricantes | ST Microelectronics | |
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STM8L101xx
8-bit ultralow power microcontroller with up to 8 Kbytes Flash,
multifunction timers, comparators, USART, SPI, I2C
Features
■ Main microcontroller features
– Supply voltage range 1.65 V to 3.6 V
– Low power consumption (Halt: 0.3 µA,
Active-halt: 0.8 µA, Dynamic Run:
150 µA/MHz)
– STM8 Core with up to 16 CISC MIPS
throughput
– Temp. range: -40 to 85 °C and 125 °C
■ Memories
– Up to 8 Kbytes of Flash program including
up to 2 Kbytes of data EEPROM
– Error correction code (ECC)
– Flexible write and read protection modes
– In-application and in-circuit programming
– Data EEPROM capability
– 1.5 Kbytes of static RAM
■ Clock management
– Internal 16 MHz RC with fast wakeup time
(typ. 4 µs)
– Internal low consumption 38 kHz RC
driving both the IWDG and the AWU
■ Reset and supply management
– Ultralow power, ultrasafe power-on-reset
/power down reset
– Three low power modes: Wait, Active-halt,
Halt
■ Interrupt management
– Nested interrupt controller with software
priority control
– Up to 29 external interrupt sources
■ I/Os
– Up to 30 I/Os, all mappable on external
interrupt vectors
– I/Os with prog. input pull-ups, high
sink/source capability and one LED driver
infrared output
UFQFPN32
LQFP32
UFQFPN28
UFQFPN20
TSSOP20
■ Peripherals
– Two 16-bit general purpose timers (TIM2
and TIM3) with up and down counter and 2
channels (used as IC, OC, PWM)
– One 8-bit timer (TIM4) with 7-bit prescaler
– Infrared remote control (IR)
– Independent watchdog
– Auto-wakeup unit
– Beeper timer with 1, 2 or 4 kHz frequencies
– SPI synchronous serial interface
– Fast I2C Multimaster/slave 400 kHz
– USART with fractional baud rate generator
– 2 comparators with 4 inputs each
■ Development support
– Hardware single wire interface module
(SWIM) for fast on-chip programming and
non intrusive debugging
– In-circuit emulation (ICE)
■ 96-bit unique ID
Table 1. Device summary
Reference
Part number
STM8L101xx
STM8L101F2, STM8L101F3,
STM8L101G2, STM8L101G3
STM8L101K3
July 2010
Doc ID 15275 Rev 10
1/80
www.st.com
1
1 page  
STM8L101xx
List of figures
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List of figures
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Figure 46.
STM8L101xx device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Standard 20-pin UFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
20-pin UFQFPN package pinout for STM8L101F3U6ATR and
STM8L101F2U6ATR part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
20-pin TSSOP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Standard 28-pin UFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
28-pin UFQFPN package pinout for STM8L101G3U6ATR and
STM8L101G2U6ATR part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
32-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
IDD(RUN) vs. VDD, fCPU = 2 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
IDD(WAIT) vs. VDD, fCPU = 2 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
IDD(WAIT) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Typ. IDD(Halt) vs. VDD, fCPU = 2 MHz and 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Typical HSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Typical HSI accuracy vs. temperature, VDD = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Typical HSI accuracy vs. temperature, VDD = 1.65 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . 47
Typical LSI RC frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Typical VIL and VIH vs. VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Typical pull-up resistance RPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Typical pull-up current IPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Typ. VOL at VDD = 3.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Typ. VOL at VDD = 1.8 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Typ. VOL at VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Typ. VOL at VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Typ. VDD - VOH at VDD = 3.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Typ. VDD - VOH at VDD = 1.8 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Typical NRST pull-up resistance RPU vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Typical NRST pull-up current Ipu vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5 x 5). . . . . . 67
UFQFPN32 recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LQFP32 - 32-pin low profile quad flat package outline (7 x 7) . . . . . . . . . . . . . . . . . . . . . . 69
LQFP32 recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package outline (4 x 4)(1) . . . . 70
UFQFPN28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
UFQFPN20 3 x 3 mm 0.6 mm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
UFQFPN20 recommended footprint (1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
TSSOP20 - 20-lead thin shrink small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
TSSOP20 recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Doc ID 15275 Rev 10
5/80
5 Page 
STM8L101xx
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Product overview
3.5 Memory
The STM8L101xx devices have the following main features:
● 1.5 Kbytes of RAM
● The EEPROM is divided into two memory arrays (see the STM8L reference manual for
details on the memory mapping):
– Up to 8 Kbytes of low-density embedded Flash program including up to 2 Kbytes
of data EEPROM. Data EEPROM and Flash program areas can be write protected
independently by using the memory access security mechanism (MASS).
– 64 option bytes (one block) of which 5 bytes are already used for the device.
Error correction code is implemented on the EEPROM.
3.6 Low power modes
To minimize power consumption, the product features three low power modes:
● Wait mode: CPU clock stopped, selected peripherals at full clock speed.
● Active-halt mode: CPU and peripheral clocks are stopped. The programmable wakeup
time is controlled by the AWU unit.
● Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.
Wakeup is triggered by an external interrupt.
3.7 Voltage regulators
The STM8L101xx embeds an internal voltage regulator for generating the 1.8 V power
supply for the core and peripherals.
This regulator has two different modes: main voltage regulator mode (MVR) and low power
voltage regulator mode (LPVR). When entering Halt or Active-halt modes, the system
automatically switches from the MVR to the LPVR in order to reduce current consumption.
3.8 Clock control
The STM8L101xx embeds a robust clock controller. It is used to distribute the system clock
to the core and the peripherals and to manage clock gating for low power modes. This
system clock is a 16-MHz High Speed Internal RC oscillator (HSI RC), followed by a
programmable prescaler.
In addition, a 38 kHz low speed internal RC oscillator is used by the independent watchdog
(IWDG) and Auto-wakeup unit (AWU).
3.9 Independent watchdog
The independent watchdog (IWDG) peripheral can be used to resolve processor
malfunctions due to hardware or software failures.
It is clocked by the 38 kHZ LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure.
Doc ID 15275 Rev 10
11/80
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet STM8L101G2.PDF ] | |
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