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Número de pieza | LP62P16128CV-12LLT | |
Descripción | 128K X 16 BIT LOW VOLTAGE CMOS SRAM | |
Fabricantes | AMIC Technology | |
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No Preview Available ! LP62P16128C-T Series
Preliminary
128K X 16 BIT LOW VOLTAGE CMOS SRAM
Document Title
128K X 16 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
March 11, 2002
Remark
Preliminary
PRELIMINARY (March, 2002, Version 0.0)
AMIC Technology, Inc.
1 page LP62P16128C-T Series
Absolute Maximum Ratings*
VCC to GND ...............................................-0.5V to +4.6V
IN, IN/OUT Volt to GND .................... -0.5V to VCC + 0.5V
Operating Temperature, Topr ....................-25°C to +85°C
Storage Temperature, Tstg......................-55°C to +125°C
Power Dissipation, PT ............................................... 0.7W
*Comments
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = -25°C to + 85°C, VCC = 2.3V to 2.7V, GND = 0V)
Symbol
Parameter
ILI Input Leakage Current
Output Leakage Current
ILO
ICC Active Power Supply Current
ICC1
Dynamic Operating Current
ICC2
ISB
Standby Power
ISB1 Supply Current
VOL Output Low Voltage
VOH Output High Voltage
LP62P16128C-12LLT
Min.
-
Max.
1
-1
-3
- 20
-4
- 0.3
- 100
- 0.4
1.8 -
Unit Conditions
µA VIN = GND to VCC
CE = VIH or
µA LB = HB = VIH
VI/O = GND to VCC
CE = VIL ,
mA
LB = VIL or HB = VIL , II/O = 0 mA
Min. Cycle, Duty = 100%
mA CE = VIL,
LB = VIL or HB = VIL, II/O = 0 mA
CE ≤ 0.2V ,
mA LB ≤ 0.2V or HB ≤ 0.2V,
f = 1MHz , II/O = 0 mA
mA CE = VIH or LB = HB = VIH
CE ≥ VCC – 0.2V or
µA LB = HB ≥ VCC – 0.2V,
VIN ≥ VCC – 0.2V or VIN ≤ 0.2V
V IOL = 2.1 mA
V IOH = -1.0 mA
PRELIMINARY (March, 2002, Version 0.0)
4
AMIC Technology, Inc.
5 Page Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
Address
CE
HB, LB
tAS1
WE
DATA IN
DATA OUT
tWHZ4
LP62P16128C-T Series
tWC
tAW
tCW
tBW2
tWP
tDW
tWR3
tDH
tOW
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and ( HB and , or LB ).
3. tWR is measured from the earliest of CE or WE or ( HB and , or LB ) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (March, 2002, Version 0.0)
10
AMIC Technology, Inc.
11 Page |
Páginas | Total 15 Páginas | |
PDF Descargar | [ Datasheet LP62P16128CV-12LLT.PDF ] |
Número de pieza | Descripción | Fabricantes |
LP62P16128CV-12LLT | 128K X 16 BIT LOW VOLTAGE CMOS SRAM | AMIC Technology |
LP62P16128CV-12LLT | 128K X 16 BIT LOW VOLTAGE CMOS SRAM | AMIC Technology |
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