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PDF LPC2124 Data sheet ( Hoja de datos )
| Número de pieza | LPC2124 | |
| Descripción | Single-chip 16/32-bit microcontrollers; 128/256 kB ISP/IAP fash | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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LPC2114/2124
Single-chip 16/32-bit microcontrollers; 128/256 kB ISP/IAP
flash with 10-bit ADC
Rev. 06 — 10 December 2007
Product data sheet
1. General description
The LPC2114/2124 are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation
and embedded trace support, together with 128/256 kB of embedded high-speed flash
memory. A 128-bit wide memory interface and a unique accelerator architecture enable
32-bit code execution at maximum clock rate. For critical code size applications, the
alternative 16-bit Thumb mode reduces code by more than 30 % with minimal
performance penalty.
With their compact 64-pin package, low power consumption, various 32-bit timers,
4-channel 10-bit ADC, PWM channels and 46 fast GPIO lines with up to nine external
interrupt pins these microcontrollers are particularly suitable for industrial control, medical
systems, access control and point-of-sale. With a wide range of serial communications
interfaces, they are also very well suited for communication gateways, protocol converters
and embedded soft modems as well as many other general-purpose applications.
Remark: Throughout the data sheet, the term LPC2114/2124 will apply to devices with
and without the /00 or /01 suffixes. The /00 or the /01 suffix will be used to differentiate
from other devices only when necessary.
2. Features
2.1 Key features brought by LPC2114/2124/01 devices
I Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original device.
They also allow for a port pin to be read at any time regardless of its function.
I Dedicated result registers for ADC(s) reduce interrupt overhead. The ADC pads are
5 V tolerant when configured for digital I/O function(s).
I UART0/1 include fractional baud rate generator, auto-bauding capabilities and
handshake flow-control fully implemented in hardware.
I Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.
I SPI programmable data length and master mode enhancement.
I Diversified Code Read Protection (CRP) enables different security levels to be
implemented. This feature is available in LPC2114/2124/00 devices as well.
I General purpose timers can operate as external event counters.
2.2 Key features common for all devices
I 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
I 16 kB on-chip static RAM.
1 page  
NXP Semiconductors
5. Pinning information
5.1 Pinning
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LPC2114/2124
Single-chip 16/32-bit microcontrollers
P0[21]/PWM5/CAP1[3] 1
P0[22]/CAP0[0]/MAT0[0] 2
P0[23] 3
P1[19]/TRACEPKT3 4
P0[24] 5
VSS
VDDA(3V3)
P1[18]/TRACEPKT2
6
7
8
P0[25] 9
n.c. 10
P0[27]/AIN0/CAP0[1]/MAT0[1] 11
P1[17]/TRACEPKT1 12
P0[28]/AIN1/CAP0[2]/MAT0[2] 13
P0[29]/AIN2/CAP0[3]/MAT0[3] 14
P0[30]/AIN3/EINT3/CAP0[0] 15
P1[16]/TRACEPKT0 16
LPC2114
LPC2124(1)
48 P1[20]/TRACESYNC
47 P0[17]/CAP1[2]/SCK1/MAT1[2]
46 P0[16]/EINT0/MAT0[2]/CAP0[2]
45 P0[15]/RI1/EINT2
44 P1[21]/PIPESTAT0
43 VDD(3V3)
42 VSS
41 P0[14]/DCD1/EINT1
40 P1[22]/PIPESTAT1
39 P0[13]/DTR1/MAT1[1]
38 P0[12]/DSR1/MAT1[0]
37 P0[11]/CTS1/CAP1[1]
36 P1[23]/PIPESTAT2
35 P0[10]/RTS1/CAP1[0]
34 P0[9]/RXD1/PWM6/EINT3
33 P0[8]/TXD1/PWM4
002aad176
(1) Pin configuration is identical for devices with and without the /00 and /01 suffixes.
Fig 2. Pin configuration
LPC2114_2124_6
Product data sheet
Rev. 06 — 10 December 2007
© NXP B.V. 2007. All rights reserved.
5 of 40
5 Page 
NXP Semiconductors
www.DataSheet4U.com
LPC2114/2124
Single-chip 16/32-bit microcontrollers
However, the ISP flash erase command can be executed at any time (no matter whether
the CRP is on or off). Removal of CRP is achieved by erasure of full on-chip user flash.
With the CRP off, full access to the chip via the JTAG and/or ISP is restored.
6.3 On-chip static RAM
On-chip static RAM may be used for code and/or data storage. The SRAM may be
accessed as 8 bit, 16 bit, and 32 bit. The LPC2114/2124 provide 16 kB of static RAM.
6.4 Memory map
The LPC2114/2124 memory maps incorporate several distinct regions, as shown in
Figure 3.
In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either
flash memory (the default) or on-chip static RAM. This is described in Section 6.17
“System control”.
LPC2114_2124_6
Product data sheet
Rev. 06 — 10 December 2007
© NXP B.V. 2007. All rights reserved.
11 of 40
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LPC2124.PDF ] | |
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