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PDF LTC1859 Data sheet ( Hoja de datos )
| Número de pieza | LTC1859 | |
| Descripción | 100ksps SoftSpan A/D Converters | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC1859 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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LTC1857/LTC1858/LTC1859
8-Channel, 12-/14-/16-Bit,
100ksps SoftSpan A/D Converters
with Shutdown
FEATURES
■ Sample Rate: 100ksps
■ 8-Channel Multiplexer with ±25V Protection
■ Single 5V Supply
■ Software-Programmable Input Ranges:
0V to 5V, 0V to 10V, ±5V or ±10V
www.DataSShineegtl4eUE.cnodmed or Differential
■ ±3LSB INL for the LTC1859, ±1.5LSB INL for the
LTC1858, ±1LSB INL for the LTC1857
■ Power Dissipation: 40mW (Typ)
■ SPI/MICROWIRETM Compatible Serial I/O
■ Power Shutdown: Nap and Sleep
■ Signal-to-Noise Ratio: 87dB (Typ) for the LTC1859
■ Operates with Internal or External Reference
■ Internal Synchronized Clock
■ 28-Pin SSOP Package
U
APPLICATIO S
■ Industrial Process Control
■ Multiplexed Data Acquisition Systems
■ High Speed Data Acquisition for PCs
■ Digital Signal Processing
DESCRIPTIO
The LTC®1857/LTC1858/LTC1859 are 8-channel, low
power, 12-/14-/16-bit, 100ksps, analog-to-digital con-
verters (ADCs). These SoftSpanTM ADCs can be software-
programmed for 0V to 5V, 0V to 10V, ±5V or ±10V input
spans and operate from a single 5V supply. The 8-chan-
nel multiplexer can be programmed for single-ended
inputs or pairs of differential inputs or combinations of
both. In addition, all channels are fault protected to ±25V.
A fault condition on any channel will not affect the
conversion result of the selected channel.
An onboard high performance sample-and-hold and pre-
cision reference minimize external components. The low
40mW power dissipation is made even more attractive
with two user selectable power shutdown modes. DC speci-
fications include ±3LSB INL for the LTC1859, ±1.5LSB
INL for the LTC1858 and ±1LSB for the LTC1857.
The internal clock is trimmed for 5µs maximum conver-
sion time and the sampling rate is guaranteed at 100ksps.
A separate convert start input and data ready signal (BUSY)
ease connections to FIFOs, DSPs and microprocessors.
, LTC and LT are registered trademarks of Linear Technology Corporation.
SoftSpan is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
TYPICAL APPLICATIO
100kHz, 12-Bit/14-Bit/16-Bit Sampling ADC
SOFTWARE-PROGRAMMABLE
SINGLE-ENDED OR
DIFFERENTIAL INPUTS
(0V TO 5V, 0V TO 10V,
±5V OR ±10V)
COM
CONVST
CH0 LTC1857/ RD
CH1 LTC1858/ SCK
CH2 LTC1859 SDI
CH3 DGND
CH4 SDO
CH5 BUSY
CH6 OVDD
CH7
MUXOUT+
MUXOUT–
DVDD
AVDD
AGND3
ADC+
AGND2
ADC–
REFCOMP
AGND1
VREF
µP
CONTROL
LINES
10µF
10µF
1µF 10µF
3V TO 5V
5V
5V
10µF
2.5V
LTC1859 Typical INL Curve
2.0
1.5
1.0
0.5
0
– 0.5
–1.0
–1.5
–2.0
–32768 –16384
0
CODE
16384 32767
1859 TA02
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1
1 page  
LTC1857/LTC1858/LTC1859
WU
TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency
Through CH0 to CH7 Inputs
Through ADC+, ADC– Only
● 100
166
kHz
kHz
tCONV
tACQ
Conversion Time
Acquisition Time
Through CH0 to CH7 Inputs
Through ADC+, ADC– Only
●
●
4 5 µs
4 µs
1 µs
fSCK SCK Frequency
tr SDO Rise Time
tf SDO Fall Time
wwwt1.DataSheet4CUO.cNoVmST High Time
t2 CONVST to BUSY Delay
t3 SCK Period
t4 SCK High
t5 SCK Low
t6 Delay Time, SCK↓ to SDO Valid
t7 Time from Previous SDO Data Remains
Valid After SCK↓
(Note 14)
See Test Circuits
See Test Circuits
CL = 25pF, See Test Circuits
CL = 25pF, See Test Circuits
CL = 25pF, See Test Circuits
●0
20 MHz
6 ns
6 ns
● 40
ns
●
15 30
ns
● 50
ns
● 10
ns
● 10
ns
●
25 45
ns
●5
20
ns
t8 SDO Valid After RD↓
t9 RD↓ to SCK Setup Time
t10 SDI Setup Time Before SCK↑
t11 SDI Hold Time After SCK↑
t12 SDO Valid Before BUSY↑
t13 Bus Relinquish Time
CL = 25pF, See Test Circuits
●
11 30
● 20
●0
●7
RD = Low, CL = 25pF, See Test Circuits ●
5
20
See Test Circuits
● 10 30
ns
ns
ns
ns
ns
ns
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, AGND1,
AGND2 and AGND3 wired together unless otherwise noted.
Note 3: When these pin voltages are taken below ground or above AVDD =
DVDD = OVDD = VDD, they will be clamped by internal diodes. This product
can handle currents of greater than 100mA below ground or above VDD
without latchup.
Note 4: When these pin voltages are taken below ground they will be
clamped by internal diodes. This product can handle currents of greater
than 100mA below ground without latchup. These pins are not clamped
to VDD.
Note 5: VDD = 5V, fSAMPLE = 100kHz, tr = tf = 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended analog MUX input with respect to ground or ADC+ with respect to
ADC– tied to ground.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar zero error is the offset voltage measured from – 0.5LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111 for the LTC1859, between 00 0000 0000 0000 and 11
1111 1111 1111 for the LTC1858 and between 0000 0000 0000 and 1111
1111 1111 for the LTC1857. Unipolar zero error is the offset voltage
measured from 0.5LSB when the output codes flicker between 0000 0000
0000 0000 and 0000 0000 0000 0001 for the LTC1859, between 00 0000
0000 0000 and 00 0000 0000 0001 for the LTC1858 and between 0000
0000 0000 and 0000 0000 0001 for the LTC1857.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: Full-scale bipolar error is the worst case of –FS or +FS
untrimmed deviation from ideal first and last code transitions, divided by
the full-scale range, and includes the effect of offset error. For unipolar
full-scale error, the deviation of the last code transition from ideal, divided
by the full-scale range, and includes the effect of offset error.
Note 12: All Specifications in dB are referred to a full-scale ±10V input.
Note 13: Recovers to specified performance after (2 • FS) input
overvoltage.
Note 14: t6 of 45ns maximum allows fSCK up to 10MHz for rising capture
with 50% duty cycle and fSCK up to 20MHz for falling capture (with 5ns
setup time for the receiving logic).
Note 15: The specification is referred to the ±10V input range.
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5 Page 
APPLICATIO S I FOR ATIO
LTC1857/LTC1858/LTC1859
AVDD DVDD
CH0
CH1
• INPUT MUX
•
AND
RANGE
• SELECT
www.DataSheetC4HU7.com
COM
MUX ADDRESS AND RANGE
INTERNAL
CLOCK
CONTROL
LOGIC
+
12-/14-/16-BIT
SAMPLING ADC
–
DATA OUT
2.5V
REFERENCE
8k
4.096V
1.6384X
SERIAL I/O
CONVST
SDI
BUSY
SCK
RD
OVDD
SDO
MUXOUT–
AGND1
MUXOUT+ ADC+
ADC–
VREF
REFCOMP
1859 BD
AGND2 AGND3 DGND
Figure 1. LTC1857/LTC1858/LTC1859 Simplified Equivalent Circuit
AIN+ CH0
3000pF
AIN– CH1
•
•
•
•
MUXOUT+
MUXOUT–
ADC+
ADC–
1859 F02
Figure 2. Analog Input Filtering
LT1792: Single, low noise JFET input op amp, ±5V
supplies.
LT1793: Single, low noise JFET input op amp, 10pA bias
current, ±5V supplies.
LT1881/LT1882: Dual and quad, 200pA bias current, rail-
to-rail output op amps. Up to ±15V supplies.
LT1844/LT1885: Dual and quad, 400pA bias current, rail-
to-rail output op amps. Up to ±15V supplies. Faster
response and settling time.
LT1227: 140MHz video current feedback amplifier. 10mA
supply current. ±5V to ±15V supplies. Low noise and low
distortion.
LT1468/LT1469: Single and dual 90MHz, 16-bit accurate
op amp. Good AC/DC specs.
LT1677: Single, low noise op amp. Rail-to-rail input and
output. Up to ±15V supplies.
INTERNAL VOLTAGE REFERENCE
The LTC1857/LTC1858/LTC1859 have an on-chip, tem-
perature compensated, curvature corrected, bandgap ref-
erence, which is factory trimmed to 2.50V. The full-scale
range of the LTC1857/LTC1858/LTC1859 is equal to ±5V,
0V to 5V, ±10V or 0V to 10V. The output of the reference
is connected to the input of a gain of 1.6384x buffer
through an 8k resistor (see Figure 3). The input to the
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11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC1859.PDF ] | |
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