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PDF MAX5945 Data sheet ( Hoja de datos )
| Número de pieza | MAX5945 | |
| Descripción | Quad Network Power Controller | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-3428; Rev 1; 9/05
EVAALVUAAILTAIOBNLEKIT
www.DataSheet4U.com
Quad Network Power Controller
for Power-Over-LAN
General Description
The MAX5945 quad network power controller is designed
for use in IEEE 802.3af-compliant power-sourcing equip-
ment (PSE). The device provides power devices (PD) dis-
covery, classification, current-limit, and both DC and AC
load disconnect detections. The MAX5945 can be used
in either endpoint PSE (LAN switches/routers) or midspan
PSE (power injector) applications. The MAX5945 is pin
and function compatible with LTC4259A.
The MAX5945 can operate autonomously or be con-
trolled by software through an I2C*-compatible inter-
face. Separate input and output data lines (SDAIN and
SDAOUT) allow usage with optocouplers. The
MAX5945 is a slave device. Its four address inputs
allow 16 unique MAX5945 addresses. A separate INT
output and four independent shutdown inputs (SHD_)
allow fast response from a fault to port shutdown. A
RESET input allows hardware reset of the device. A
special watchdog feature allows the hardware to grace-
fully take over control if the software crashes. A
cadence timing feature allows the MAX5945 to be used
in midspan systems.
The MAX5945 is fully software configurable and program-
mable. A class-overcurrent detection function enables
system power management to detect if a PD draws more
current than the allowable amount for its class. Other fea-
tures are input under/overvoltage lockout, overtempera-
ture protection, output-voltage slew-rate limit during
startup, power-good, and fault status. The MAX5945’s
programmability includes gate-charging current, current-
limit threshold, startup timeout, overcurrent timeout,
autorestart duty cycle, PD disconnect AC detection
threshold, and PD disconnect detection timeout.
The MAX5945 is available in a 36-pin SSOP package
and is rated for both extended (-40°C to +85°C) and
commercial (0°C to +70°C) temperature ranges.
Applications
Power-Sourcing Equipment (PSE)
Power-Over-LAN/Power-Over-Ethernet
Switches/Routers
Midspan Power Injectors
*Purchase of I2C components from Maxim Integrated
Products, Inc. or one of its sublicensed Associated
Companies, conveys a license under the Philips I2C Patent
Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as
defined by Philips.
Typical Operating Circuits appear at end of data sheet.
Features
♦ IEEE 802.3af Compliant
♦ Pin and Function Compatible with LTC4259A
♦ Controls Four Independent, -48V-Powered
Ethernet Ports in Either Endpoint or Midspan PSE
Applications
♦ Wide Digital Power Input, VDIG, Common-Mode
Range: VEE to (AGND + 7.7V)
♦ PD Violation of Class Current Protection
♦ PD Detection and Classification
♦ Provides Both DC and AC Load Removal
Detections
♦ I2C-Compatible, 3-Wire Serial Interface
♦ Fully Programmable and Configurable Operation
Through I2C Interface
♦ Current Foldback and Duty-Cycle-
Controlled/Programmable Current Limit
♦ Short-Circuit Protection with Fast Gate Pulldown
♦ Direct Fast Shutdown Control Capability
♦ Programmable Direct Interrupt Output
♦ Watchdog Mode Enable Hardware Graceful
Takeover
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX5945CAX**
MAX5945EAX
0°C to +70°C
-40°C to +85°C
36 SSOP
36 SSOP
**Future product—contact factory for availability.
Pin Configuration
TOP VIEW
RESET 1
MIDSPAN 2
INT 3
SCL 4
SDAOUT 5
SDAIN 6
A3 7
A2 8
A1 9
A0 10
DET1 11
DET2 12
DET3 13
DET4 14
DGND 15
VDD 16
SHD1 17
SHD2 18
MAX5945
SSOP
36 OSC_IN
35 AUTO
34 OUT1
33 GATE1
32 SENSE1
31 OUT2
30 GATE2
29 SENSE2
28 VEE
27 OUT3
26 GATE3
25 SENSE3
24 OUT4
23 GATE4
22 SENSE4
21 AGND
20 SHD4
19 SHD3
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
www.DataSheet4U.com
Quad Network Power Controller
for Power-Over-LAN
ELECTRICAL CHARACTERISTICS (continued)
(AGND = +32V to +60V, VEE = 0V, VDD to DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical
values are at AGND = +48V, DGND = +48V, VDD = (DGND + 3.3V), TA = +25°C. Currents are positive when entering the pin and
negative otherwise.)
PARAMETER
Internal Input Pullup/Pulldown
Resistor
Open-Drain Output Low
Voltage
Open-Drain Leakage
TIMING
Startup Time
SYMBOL
CONDITIONS
RDIN
Pullup (pulldown) resistor to VDD (DGND) to set
default level
VOL ISINK = 15mA
IOL Open-drain high impedance, VO = 3.3V
tSTART
Time during which a current limit set by VSU_LIM
is allowed, starts when the GATE_
is turned on (Note 8)
MIN TYP MAX UNITS
25 50 75 kΩ
0.4 V
2 µA
50 60 70 ms
Fault Time
Port Turn-Off Time
tFAULT
tOFF
Maximum allowed time for an overcurrent
condition set by VFLT_LIM after startup (Note 8)
Minimum delay between any port turning off,
does not apply in the case of a reset
50 60 70
0.5 0.75 1.0
ms
ms
Detection Time
Midspan Mode Detection
Delay
Classification Time
VEEUVLO Turn-On Delay
tDET
Maximum time allowed before detection
is completed
tDMID
tCLASS
tDLY
Time allowed for classification
Time VAGND must be above the VEEUVLO
thresholds before the device operates
Restart Timer
RSTR bits = 00
tRESTART
Time a port has to wait
before turning on after an
overcurrent fault,
RSTR_EN bit = high
RSTR bits = 01
RSTR bits = 10
RSTR bits = 11
Watchdog Clock Period
tWD Rate of decrement of the watchdog timer
TIMING CHARACTERISTICS for 2-WIRE FAST MODE (Figures 5 and 6)
Serial Clock Frequency
fSCL (Note 9)
Bus Free Time Between a
STOP and a START Condition
tBUF (Note 9)
Hold Time for Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
tHD, STA
tLOW
tHIGH
(Note 9)
(Note 9)
(Note 9)
320
2.0 2.4
40
24
16 x
tFAULT
32 x
tFAULT
64 x
tFAULT
0
164
ms
s
ms
ms
ms
ms
400 kHz
1.2 µs
0.6 µs
1.2 µs
0.6 µs
_______________________________________________________________________________________ 5
5 Page 
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Quad Network Power Controller
for Power-Over-LAN
Pin Description
PIN NAME
FUNCTION
Hardware Reset. Pull RESET low for at least 300µs to reset the device. All internal registers reset to
1
RESET
their default value. The address (A0–A3), and AUTO and MIDSPAN input logic levels latch on during
low-to-high transition of RESET. Internally pulled up to VDD with 50kΩ resistor.
MIDSPAN Mode Input. An internal 50kΩ pulldown resistor to DGND sets the default mode to endpoint
2
MIDSPAN
PSE operation (power-over-signal pairs). Pull MIDSPAN TO VDIG to set MIDSPAN operation. The
MIDSPAN value latches after the IC is powered up or reset (see the PD Detection section).
Open-Drain Interrupt Output. INT goes low whenever a fault condition exists. Reset the fault condition
3 INT using software or by pulling RESET low (see the Interrupt section of the Detailed Description for more
information about interrupt management).
4 SCL Serial Interface Clock Line
5
SDAOUT
Serial Output Data Line. Connect the data line optocoupler input to SDAOUT (see the Typical
Application Circuit). Connect SDAOUT to SDAIN if using a 2-wire I2C-compatible system.
6
SDAIN
Serial Interface Input Data Line. Connect the data line optocoupler output SDAIN (see the Typical
Application Circuit). Connect SDAIN to SDAOUT if using a 2-wire wire I2C-compatible system.
7–10
A3, A2, A1, A0
Address Bits. A3, A2, A1, and A0 form the lower part of the device’s address. Address inputs default
high with an internal 50kΩ pullup resistor to VDD. The address values latch when VDD or VEE ramps
up and exceeds its UVLO threshold or after a reset. The 3 MSB bits of the address are set to 010.
11–14
DET1, DET2,
DET3, DET4
Detection and Classification Voltage Outputs. Use DET1 to set the detection and classification probe
voltages on port 1. Use DET1 for the AC voltage sensing of port 1 when using the AC disconnect
scheme (see the Typical Application Circuit).
15
16
17–20
21
22, 25,
29, 32
23, 26,
30, 33
DGND
Connect to Digital Ground
VDD
SHD1, SHD2,
SHD3, SHD4
Positive Digital Supply. Connect to digital supply (referenced to DGND).
Port Shutdown Inputs. Pull SHD_ low to turn off the external FET on port_. Internally pulled up to VDD
with a 50kΩ resistor.
AGND
Analog Ground. Connect to the high-side analog supply.
SENSE4, SENSE3, MOSFET Source Current-Sense Negative Inputs. Connect to the source of the power MOSFET and
SENSE2, SENSE1 connect a current-sense resistor between SENSE_ and VEE (see the Typical Application Circuit).
GATE4, GATE3, Port_ MOSFET Gate Drivers. Connect GATE_ to the gate of the external FET (see the Typical
GATE2, GATE1 Application Circuit).
24, 27,
31, 34
OUT4, OUT3,
OUT2, OUT1
MOSFET Drain-Output Voltage Senses. Connect OUT_ to the power MOSFET drain through a resistor
(100Ω to 100kΩ). The low leakage at OUT_ limits the drop across the resistor to less than 100mV
(see the Typical Application Circuit).
28
VEE
Low-Side Analog Supply Input. Connect the low-side analog supply to VEE (-48V). Bypass with a 1µF
capacitor between AGND and VEE.
AUTO or SHUTDOWN Mode Input. Force high to enter AUTO mode after a reset or power-up. Drive
low to put the MAX5945 into SHUTDOWN mode. In SHUTDOWN mode, software controls the
35
AUTO
operational modes of the MAX5945. A 50kΩ internal pulldown resistor defaults AUTO low. AUTO
latches when VDD or VEE ramps up and exceeds its UVLO threshold or when the device resets.
Software commands can take the MAX5945 out of AUTO while AUTO is high.
Oscillator Input. AC-disconnect detection function uses OSC_IN. Connect a 100Hz ±10%, 2VP-P
36
OSC_IN
±5%, +1.2V offset sine wave to OSC_IN. If the oscillator positive peak falls below the OSC_FAIL
threshold of 2V, the ports that have the AC function enabled shut down and are not allowed to power
up. When not using the AC-disconnect detection function, leave OSC_IN unconnected.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MAX5945.PDF ] | |
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