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PDF SH7785 Data sheet ( Hoja de datos )
| Número de pieza | SH7785 | |
| Descripción | 32-Bit RISC Microcomputer | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SH7785 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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REJ09B0261-0100
www.DataSheet4U.com
32
SH7785
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperH™ RISC Engine Family
SH7780 Series
Rev.1.00
Revision Date: Jan. 10, 2008
1 page  
Preface
www.DataSheet4U.com
This LSI is a RISC (Reduced Instruction Set Computer) microcomputer which includes a Renesas
Technology-original RISC CPU (SH-4A) and various peripheral functions required to configure a
system.
Target Users:This manual was written for users who will be using this LSI in the design of
application systems. Users of this manual are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective: This manual was written to explain the hardware functions and electrical
characteristics of this LSI to the above users.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual consists of parts on the CPU, system
control functions, peripheral functions and electrical characteristics.
• In order to understand individual instructions in detail
Read the separate manuals SH-4A Extended Functions Software Manual and SH-4A Software
Manual.
Rules:
Bit order:
Number notation:
Signal notation:
The MSB is on the left and the LSB is on the right.
Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
An overbar is added to active-low signals: xxxx
Rev.1.00 Jan. 10, 2008 Page v of xxx
REJ09B0261-0100
5 Page 
7.1.1 Address Spaces ................................................................................................... 146
7.2 Register Descriptions ......................................................................................................... 152
7.2.1 Page Table Entry High Register (PTEH)..................w...w..w.....D..a..t.a...S.h..e..e..t.4..U....c..o..m........ 153
7.2.2 Page Table Entry Low Register (PTEL) ............................................................. 154
7.2.3 Translation Table Base Register (TTB) .............................................................. 155
7.2.4 TLB Exception Address Register (TEA) ............................................................ 156
7.2.5 MMU Control Register (MMUCR) .................................................................... 156
7.2.6 Page Table Entry Assistance Register (PTEA)................................................... 159
7.2.7 Physical Address Space Control Register (PASCR)........................................... 160
7.2.8 Instruction Re-Fetch Inhibit Control Register (IRMCR) .................................... 162
7.3 TLB Functions (TLB Compatible Mode; MMUCR.ME = 0)............................................ 164
7.3.1 Unified TLB (UTLB) Configuration .................................................................. 164
7.3.2 Instruction TLB (ITLB) Configuration............................................................... 167
7.3.3 Address Translation Method............................................................................... 167
7.4 TLB Functions (TLB Extended Mode; MMUCR.ME = 1) ............................................... 170
7.4.1 Unified TLB (UTLB) Configuration .................................................................. 170
7.4.2 Instruction TLB (ITLB) Configuration............................................................... 173
7.4.3 Address Translation Method............................................................................... 174
7.5 MMU Functions................................................................................................................. 177
7.5.1 MMU Hardware Management............................................................................ 177
7.5.2 MMU Software Management ............................................................................. 177
7.5.3 MMU Instruction (LDTLB)................................................................................ 178
7.5.4 Hardware ITLB Miss Handling .......................................................................... 180
7.5.5 Avoiding Synonym Problems ............................................................................. 181
7.6 MMU Exceptions............................................................................................................... 182
7.6.1 Instruction TLB Multiple Hit Exception............................................................. 182
7.6.2 Instruction TLB Miss Exception......................................................................... 183
7.6.3 Instruction TLB Protection Violation Exception ................................................ 184
7.6.4 Data TLB Multiple Hit Exception ...................................................................... 185
7.6.5 Data TLB Miss Exception .................................................................................. 185
7.6.6 Data TLB Protection Violation Exception.......................................................... 187
7.6.7 Initial Page Write Exception............................................................................... 188
7.7 Memory-Mapped TLB Configuration................................................................................ 190
7.7.1 ITLB Address Array ........................................................................................... 191
7.7.2 ITLB Data Array (TLB Compatible Mode)........................................................ 192
7.7.3 ITLB Data Array (TLB Extended Mode) ........................................................... 193
7.7.4 UTLB Address Array.......................................................................................... 195
7.7.5 UTLB Data Array (TLB Compatible Mode) ...................................................... 196
7.7.6 UTLB Data Array (TLB Extended Mode).......................................................... 197
7.8 32-Bit Address Extended Mode ......................................................................................... 199
Rev.1.00 Jan. 10, 2008 Page xi of xxx
REJ09B0261-0100
11 Page | ||
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