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PDF MX28F640C3T Data sheet ( Hoja de datos )
| Número de pieza | MX28F640C3T | |
| Descripción | 64M-BIT [4M x16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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ADVANCED INFORMATION
www.DataSheet4U.com
MX28F640C3T/B
FEATURES
• Bit Organization: 4,194,304 x 16
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
- VCC=VCCQ=2.7~3.6V
- Operating temperature:-40°C~85°C
• Fast access time : 90/120ns
• Low power consumption
- 9mA maximum active read current, f=5MHz (CMOS
input)
- 21mA program erase current maximum
(VPP=1.65~3.6V)
- 7uA typical standby current under power saving
mode
• Sector architecture
- Sector Erase (Sector structure : 4Kword x 2 (boot
sectors), 4Kword x 6 (parameter sectors), 32Kword x
127 (parameter sectors)
- Top/Bottom Boot
• Auto Erase (chip & sector) and Auto Program
- Automatically program and verify data at specified
address
64M-BIT [4M x16] CMOS SINGLE VOLTAGE
3V ONLY FLASH MEMORY
• Automatic Suspend Enhance
- Word write suspend to read
- Sector erase suspend to word write
- Sector erase suspend to read register report
• Automatic sector erase, full chip erase, word write and
sector lock/unlock configuration
• Status Reply
- Detection of program and erase operation comple-
tion.
- Command User Interface (CUI)
- Status Register (SR)
• Data Protection Performance
- Include boot sectors and parameter and main sectors
to be block/unblock
• 100,000 minimum erase/program cycles
• Common Flash Interface (CFI)
• 128-bit Protection Register
- 64-bit Unique Device Identifier
- 64-bit User-Programmable
• Latch-up protected to 100mA from -1V to VCC+1V
• Package type:
- 48-pin TSOP (12mm x 20mm)
- 48-ball CSP (11mm x 12mm)
GENERAL DESCRIPTION
The MX28F640C3T/B is a 64-mega bit Flash memory
organized as 4M words of 16 bits. The 1M word of data
is arranged in eight 4Kword boot and parameter sectors,
and 127 32Kword main sector which are individually
erasable. MXIC's Flash memories offer the most cost-
effective and reliable read/write non-volatile random ac-
cess memory. The MX28F640C3T/B is packaged in 48-
pin TSOP and 48-ball CSP. It is designed to be repro-
grammed and erased in system or in standard EPROM
programmers.
The standard MX28F640C3T/B offers access time as
fast as 90ns, allowing operation of high-speed micropro-
cessors without wait states.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX28F640C3T/B uses a command register to manage
this functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
P/N:PM0900
REV. 0.6, AUG. 20, 2003
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MX28F640C3T/B
Table 1. Pin Description
Symbol
A0-A21
Q0-Q15
CE
RESET
WE
VPP
OE
WP
VCC
VCCQ
GND
Type
input
input/output
input
input
input
input/supply
input
input
supply
input
supply
Description and Function
Address inputs for memory address. Data pin float to high-impedance when the chip is
deselected or outputs are disable. Addresses are internally latched during a write or
erase cycle.
Data inputs/outputs: Inputs array data on the second CE and WE cycle during a pro-
gram command. Data is internally latched. Outputs array and configuration data. The
data pin float to tri-state when the chip is de-selected.
Activates the device's control logic, input buffers, and sense amplifiers. CE high de-
selects the memory device and reduce power consumption to standby level. CE is
active low.
Reset Deep Power Down: when RESET=VIL, the device is in reset/deep power down
mode, which drives the outputs to High Z, resets the WSM and minimizes current level.
When RESET=VIH, the device is normal operation. When RESET transition the device
defaults to the read array mode.
Write Enable: to control write to CUI and array sector. WR=VIL becomes active. The
data and address is latched WE on the rising edge of the second WE pulse.
Program/Erase Power Supply:(1.65V~3.6V)
Lower VPP<VPPLK, to protect any contents against Program and Erase Command.
Set VPP=VCC for in-system Read, Program and Erase Operation.
Output enable: gates the device's outputs during a real cycle.
Write protect: when WP is VIL, the boot sectors cannot be written or erased. When WP
is VIH, locked boot sectors cannot be written or erase. WP is not affected parameter
and main sectors.
Device power supply: (2.7V~3.6V).
I/O Power Supply: supplies for input/output buffers.
[2.7V~3.6V] This input should be tied directly to VCC.
Ground voltage: all the GND pin shall not be connected.
P/N:PM0900
REV. 0.6, AUG. 20, 2003
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MX28F640C3T/B
and output high impedance state.
In read modes, RESET-low deselects the memory,
places output drivers in a high-impedance state and turns
off all internal circuits. RESET must be held low for a
minimum of 100ns.Time tPHQV is required after return
from reset mode until initial memory access outputs are
valid. After this wake-up interval tPHEL or tPHWL, nor-
mal operation is restored.The CUI is reset to read array
mode and status register is set to 80H. Sector lock bit is
set at lock status.
During sector erase, word write or sector lock/unlock
modes, RESET-low will abort the operation. Memory con-
tents being altered are no longer valid; the data may be
partially erased or written.
In addition, CUI will go into either array read mode or
erase/write interrupted mode.When power is up and the
device reset subsequently, it is necessary to read sta-
tus register in order to assure the status of the device.
Recognizing status register (SR.7~0) will assure if the
device goes back to normal reset and enters array read
mode.
mands require the command and address within the de-
vice or sector within the device (Sector Lock) to be
locked. The Clear Sector Lock-Bits command requires
the command and address within the device.
The CUI does not occupy an addressable memory loca-
tion. It is written when WE and CE are active (whichever
goes high first). The address and data needed to ex-
ecute a command are latched on the rising edge of WE
or CE. Standard microprocessor write timings are used.
3.5 Read Configuration Codes
The read configuration codes operation outputs the manu-
facturer code, device code, sector lock configuration
codes, and the protection register Using the manufac-
turer and device codes, the system CPU can automati-
cally match the device with its proper algorithms. The
sector lock codes identify locked and unlocked sectors.
3.6 Write
Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection
and clearing of the status register.When VCC=2.7V-3.6V
and VPP=VPPH1/2, the CUI additionally controls sec-
tor erase, full chip erase, word write and sector lock/
unlock.
The Sector Erase command requires appropriate com-
mand data and an address within the sector to be erased.
The Full Chip Erase command requires appropriate com-
mand data and an address within the device. The Word
Write command requires the command and address of
the location to be written. Set Sector lock/unlock com-
P/N:PM0900
REV. 0.6, AUG. 20, 2003
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