|
|
PDF HT82M9AA Data sheet ( Hoja de datos )
| Número de pieza | HT82M9AA | |
| Descripción | USB Mouse Encoder 8-Bit MCU | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HT82M9AA (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
HT82M9AE/HT82wwMw.9DaAtaSAheet4U.com
USB Mouse Encoder 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Flexible total solution for applications that combine
PS/2 and low-speed USB interface, such as mice,
joysticks, and many others
· USB Specification Compliance
- Conforms to USB specification V2.0
- Conforms to USB HID specification V2.0
· Supports 1 low-speed USB control endpoint and
2 interrupt endpoint
· Each endpoint has 8 bytes FIFO
· Integrated USB transceiver
· 3.3V regulator output
· External 6MHz or 12MHz ceramic resonator or crystal
· 8-bit RISC microcontroller, with 4K´15 program
memory (000H~FFFH)
· 224 bytes RAM (20H~FFH)
· 6MHz/12MHz internal CPU clock
· 4-level stacks
· Two 8-bit indirect addressing registers
· One 16-bit programmable timer counter with
overflow interrupt (shared with PA7, vector 0CH)
· One USB interrupt input (vector 04H)
· HALT function and wake-up feature reduce power
consumption
· PA0~PA7, PB4 and PB7 support wake-up function
· Internal Power-On reset (POR)
· Watchdog Timer (WDT)
· 16 I/O ports
· 20-pin SOP/SSOP package
24-pin SSOP package
32-pin QFN package
General Description
The USB MCU OTP body is suitable for USB mouse
and USB joystick devices. It consists of a Holtek high
performance 8-bit MCU core for control unit, built-in
USB SIE, 4K´15 ROM and 224 bytes data RAM.
The mask version HT82M9AA is fully pin and functionally
compatible with the OTP version HT82M9AE device.
Rev. 1.90
1 October 21, 2009
1 page  
HT82M9AE/HwTw8w2.DMat9aAShAeet4U.com
Functional Description
Execution Flow
The system clock for the microcontroller is derived from
either 6MHz or 12MHz crystal oscillator, which used a
frequency that is determined by the SCLKSEL bit of the
SCC Register. The default system frequency is 12MHz.
The system clock is internally divided into four non-
overlapping clocks. One instruction cycle consists of
four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to be effectively executed in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
Program Counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of pro-
gram memory.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading to the PCL register, performing a sub-
routine call or return from subroutine, initial reset,
internal interrupt, external interrupt or return from inter-
rupts, the PC manipulates the program transfer by load-
ing the address corresponding to each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within the current program ROM page.
When a control transfer takes place, an additional
dummy cycle is required.
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
S y s te m C lo c k
O S C 2 ( R C o n ly )
PC PC
PC +1 PC +2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
Execution Flow
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Mode
Program Counter
*11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
Initial Reset
000000000000
USB Interrupt
000000000100
Timer/Event Counter Overflow 0 0 0 0 0 0 0 0 1 1 0 0
Skip
Program Counter+2
Loading PCL
*11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch
#11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from Subroutine
S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Note: *11~*0: Program counter bits
#11~#0: Instruction code bits
Program Counter
S11~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.90
5 October 21, 2009
5 Page 
HT82M9AE/HwTw8w2.DMat9aAShAeet4U.com
S y s te m C lo c k /4
W DT
O SC
ROM
C ode
O p tio n
S e le c t
8 - b it C o u n te r
W D T P r e s c a le r
7 - b it C o u n te r
8 -to -1 M U X
W S 0~W S 2
W D T T im e - o u t
Watchdog Timer
If the device operates in a noisy environment, using the
on-chip 32kHz RC oscillator (WDT OSC) is strongly rec-
ommended, since the HALT will stop the system clock.
WS2 WS1 WS0
Division Ratio
000
1:1
001
1:2
010
1:4
011
1:8
100
1:16
101
1:32
110
1:64
111
1:128
WDTS (09H) Register
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit ²TO². But in the
HALT mode, the overflow will initialize a ²warm reset²
and only the program counter and SP are reset to zero.
To clear the contents of the WDT (including the WDT
prescaler), three methods are adopted; external reset (a
low level to RES), software instruction and a ²HALT² in-
struction. The software instruction include ²CLR WDT²
and the other set - ²CLR WDT1² and ²CLR WDT2². Of
these two types of instruction, only one can be active de-
pending on the ROM code option - ²CLR WDT times se-
lection option². If the ²CLR WDT² is selected (i.e.
CLRWDT times is equal to one), any execution of the
²CLR WDT² instruction will clear the WDT. In the case
that ²CLR WDT² and ²CLR WDT² are chosen (i.e.
CLRWDT times is equal to two), these two instructions
must be executed to clear the WDT; otherwise, the WDT
may reset the chip as a result of time-out.
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following:
· The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
· The contents of the on-chip RAM and registers remain
unchanged.
· The WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
· All of the I/O ports remain in their original status.
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a ²warm reset². After the TO and PDF flags are
examined, the cause for chip reset can be determined.
The PDF flag is cleared by a system power-up or exe-
cuting the ²CLR WDT² instruction and is set when exe-
cuting the ²HALT² instruction. The TO flag is set if the
WDT time-out occurs, and causes a wake-up that only
resets the program counter and SP; the others remain in
their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by mask option. Awakening from an I/O port stim-
ulus, the program will resume execution of the next in-
struction. If it awakens from an interrupt, two sequence
may occur. If the related interrupt is disabled or the inter-
rupt is enabled but the stack is full, the program will re-
sume execution at the next instruction. If the interrupt is
enabled and the stack is not full, the regular interrupt re-
sponse takes place. If an interrupt request flag is set to
²1² before entering the HALT mode, the wake-up func-
tion of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 tSYS (system clock
period) to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Rev. 1.90
11 October 21, 2009
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HT82M9AA.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HT82M9AA | USB Mouse Encoder 8-Bit MCU | Holtek Semiconductor |
| HT82M9AAE | USB Mouse Encoder 8-Bit MCU with EEPROM | Holtek Semiconductor |
| HT82M9AE | USB Mouse Encoder 8-Bit MCU | Holtek Semiconductor |
| HT82M9AEE | USB Mouse Encoder 8-Bit MCU with EEPROM | Holtek Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |