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PDF AS1153 Data sheet ( Hoja de datos )
| Número de pieza | AS1153 | |
| Descripción | Single/Dual LVDS Receivers | |
| Fabricantes | austriamicrosystems AG | |
| Logotipo |  |
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AS1153/55/57/58
Single/Dual LVDS Receivers
Data Sheet
1 General Description
The AS1153/55/57/58 are Single/Dual flow-through
LVDS (low-voltage differential signaling) receivers which
accept LVDS differential inputs and convert them to
LVCMOS outputs. The receivers are perfect for low-
power low-noise applications requiring high signaling
rates and reduced EMI emissions.
The devices are guaranteed to receive data at speeds
up to 260Mbps (130MHz) over controlled impedance
media of approximately 100Ω. Supported transmission
media are PCB traces, backplanes, and cables.
The AS1155/58 are single LVDS receivers, and the
AS1153/57 are dual LVDS receivers.
The AS1157/58 features integrated parallel termination
resistors (nominally 107Ω), which eliminate the require-
ment for discrete termination resistors, and reduce stub
lengths. The AS1153/55 uses high impedance inputs
and requires an external termination resistor when used
in a point-to-point connection.
The integrated Failsafe feature sets the output high if the
inputs are open, undriven and terminated, or undriven
and shorted.
All inputs conform to the ANSI TIA/EIA- 644 LVDS stan-
dards. Flow-through pinout simplifies PC board layout
and reduces crosstalk by separating the LVDS inputs
and LVCMOS outputs.
The devices are available in a 8-pin SOIC package.
2 Key Features
! Flow-Through Pinout
! Guaranteed 260Mbps Data Rate
! 300ps Pulse Skew (Max)
! Conform to ANSI TIA/EIA-644 LVDS Standards
! Single +3.3V Supply
! Operating Temperature Range: -40 to +85ºC
! Failsafe Circuit
! Integrated Termination (AS1157/58)
! 8-pin SOIC Package
3 Applications
Digital Copiers, Laser Printers, Cellular Phone Base Sta-
tions, Add/Drop Muxes, Digital Cross-Connects,
DSLAMs, Network Switches/Routers, Backplane Inter-
connect, Clock Distribution Computers, Intelligent Instru-
ments, Controllers, Critical Microprocessors and
Microcontrollers, Power Monitoring, and Portable/Bat-
tery-Powered Equipment.
Figure 1. Block Diagrams
AS1155/58
IN1- VCC
IN1+
OUT1
N/C N/C
N/C GND
AS1153/57
IN1-
VCC
IN1+
OUT1
IN2+
IN2-
OUT2
GND
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1 page  
AS1153/55
Data Sheet - Electrical Characteristics
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AC Electrical Characteristics
VCC = +3.0 to +3.6V, CLOAD = 10pF, Differential Input Voltage |VID| = 0.2 to 1.0V, Common-Mode Voltage VCM = |VID/2|
to 2.4V -|VID/2|, Input Rise and Fall Time = 1ns (20 to 80%), Input Frequency = 100MHz, TAMB = -40 to +85ºC. Typical
values are at VCC = +3.3V, VCM = 1.2V, |VID| = 0.2V, TAMB = +25ºC (unless otherwise specified). 1, 2
Table 4. AC Electrical Characteristics
Parameter
Symbol
Conditions
Min Typ Max Unit
Differential Propagation Delay High-
to-Low
tPHLD
Figure 20 on page 11 and Figure 21 on
page 12
1
1.8 3.1 ns
Differential Propagation Delay Low-
to-High
tPLHD
Figure 20 on page 11 and Figure 21 on
page 12
1
1.8 3.1 ns
Differential Pulse Skew
(tPHLD - tPLHD) 3
tSKD1
Figure 20 on page 11 and Figure 21 on
page 12
250 600 ps
Differential Channel-to-Channel
Skew 4
tSKD2
Figure 20 on page 11 and Figure 21 on
page 12
600 ps
Differential Part-to-Part Skew 5
tSKD3
Figure 20 on page 11 and Figure 21 on
page 12
0.8 ns
Differential Part-to-Part Skew 6
tSKD4
Figure 20 on page 11 and Figure 21 on
page 12
1.5 ns
Rise Time
tTLH
Figure 20 on page 11 and Figure 21 on
page 12
0.4 1.0 ns
Fall Time
tTHL
Figure 20 on page 11 and Figure 21 on
page 12
0.4 1.0 ns
Maximum Operating Frequency 7, 8 fMAX
All Channels Switching
130 160
MHz
Notes:
1. AC parameters are guaranteed by design and characterization.
2. CL includes scope probe and test jig capacitance.
3. tSKD1 is the magnitude difference of differential propagation delays in a channel. tSKD1 = |tPHLD - tPLHD|.
4. tSKD2 is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of any other chan-
nel on the same device.
5. tSKD3 is the magnitude difference of any differential propagation delays between devices operating over rated
conditions at the same VCC and within 5ºC of each other.
6. tSKD4 is the magnitude difference of any differential propagation delays between devices operating over rated
conditions.
7. fMAX generator output conditions:
a. Rise time = fall time = 1ns (0 to 100%)
b. 50% duty cycle
c. VOH = +1.3V
d. VOL = +1.1V
8. Output criteria:
a. Duty cycle = 60% to 40%
b. VOL = 0.4V (max)
c. VOH = 2.7V (min)
d. Load = 10pF
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AS1153/55
Data Sheet - Applications
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! Use cables and connectors with matched differential impedance (typically 100Ω) to minimize impedance mis-
matches.
! Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic
field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
! Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable.
Termination
Due to the high data rates of LVDS drivers, matched termination will prevent the generation of any signal reflections,
and reduce EMI.
! The AS1157/58 has integrated termination resistors connected across the inputs of each receiver. The value of the
integrated resistor is specified in Table 3.
! The AS1153/55 requires an external termination resistor. The termination resistor should match the differential
impedance of the transmission line and be placed as close to the receiver inputs as possible. Termination resis-
tance values may range between 90 to 132Ω depending on the characteristic impedance of the transmission
medium. Use 1% surface-mount resistors.
Board Layout
The device should be placed as close to the interface connector as possible to minimize LVDS trace length.
! Keep the LVDS and any other digital signals separated from each other to reduce crosstalk.
! Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals.
! Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent
coupling.
! Separate the input LVDS signals from the output signals planes with the power and ground planes for best results.
Figure 20. Propagation Delay and Transition Time Test Circuit
Pulse
Generator**
INx+
INx-
OUT
CL
50Ω 50Ω
Receiver
AS1153/55, AS1157/58
* 50Ω required for pulse generator.
** When testing the AS1157/58, adjust the pulse generator out-
put to account for internal termination resistor.
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