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PDF MC9S08LL36 Data sheet ( Hoja de datos )
| Número de pieza | MC9S08LL36 | |
| Descripción | (MC9S08LL36 / MC9S08LL64) 8-Bit HCS08 Central Processor Unit | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
Data Sheet: Technical Data
An Energy Efficient Solution by Freescale
MC9S08LL64 Series
Covers: MC9S08LL64 and MC9S08LL36
Document Number: MC9S08LL64
Rev. 4, 08/2009
64-LQFP
Case 840F
80-LQFP
Case 917A
• 8-Bit HCS08 Central Processor Unit (CPU)
– Up to 40 MHz CPU at 3.6 V to 2.1 V across temperature range
of –40 °C to 85 °C
– Up to 20 MHz at 2.1 V to 1.8 V across temperature range of
–40 °C to 85 °C
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources
• On-Chip Memory
– Dual array flash read/program/erase over full operating
voltage and temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM and
flash contents
• Power-Saving Modes
– Two low-power stop modes
– Reduced-power wait mode
– Low-power run and wait modes allow peripherals to run while
voltage regulator is in standby
– Peripheral clock gating register can disable clocks to unused
modules, thereby reducing currents
– Very low-power external oscillator that can be used in stop2 or
stop3 modes to provide accurate clock source to time-of-day
(TOD) module
– 6 μs typical wakeup time from stop3 mode
• Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator; crystal
or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz
to 16 MHz
– Internal Clock Source (ICS) — Internal clock source module
www.DataSheceotn4tUai.ncionmg a frequency-locked-loop (FLL) controlled by
internal or external reference; precision trimming of internal
reference allows 0.2% resolution and 2% deviation over
temperature and voltage; supporting bus frequencies from
1 MHz to 20 MHz
• System Protection
– Watchdog computer operating properly (COP) reset with
option to run from dedicated 1 kHz internal clock source or bus
clock
– Low-voltage warning with interrupt
– Low-voltage detection with reset or interrupt
– Illegal opcode detection with reset; illegal address detection
with reset
– Flash block protection
• Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus two more breakpoints in on-chip
debug module)
– On-chip in-circuit emulator (ICE) debug module containing
three comparators and nine trigger modes
• Peripherals
– LCD — Up to 8×36 or 4×40 LCD driver with internal charge
pump and option to provide an internally-regulated LCD
reference that can be trimmed for contrast control
– ADC —10-channel, 12-bit resolution; up to 2.5 μs conversion
time; automatic compare function; temperature sensor;
operation in stop3; fully functional from 3.6 V to 1.8 V
– IIC — Inter-integrated circuit bus module to operate at up to
100 kbps with maximum bus loading; multi-master operation;
programmable slave address; interrupt-driven byte-by-byte
data transfer; broadcast mode; 10-bit addressing
– ACMP — Analog comparator with selectable interrupt on
rising, falling, or either edge of comparator output; compare
option to fixed internal reference voltage; outputs can be
optionally routed to TPM module; operation in stop3
– SCIx — Two full-duplex non-return to zero (NRZ) modules
(SCI1 and SCI2); LIN master extended break generation; LIN
slave extended break detection; wakeup on active edge
– SPI — Full-duplex or single-wire bidirectional;
double-buffered transmit and receive; master or slave mode;
MSB-first or LSB-first shifting
– TPMx — Two 2-channel (TPM1 and TPM2); selectable input
capture, output compare, or buffered edge- or center-aligned
PWM on each channel
– TOD — (Time-of-day) 8-bit, quarter second counter with
match register; external clock source for precise time base,
time-of-day, calendar, or task scheduling functions
– VREFx — Trimmable via an 8-bit register in 0.5 mV steps;
automatically loaded with room temperature value upon reset;
can be enabled to operate in stop3 mode; trim register is not
available in stop modes.
• Input/Output
– Dedicated accurate voltage reference output pin, 1.2 V output
(VREFOx); trimmable with 0.5 mV resolution
– Up to 39 GPIOs, two output-only pins
– Hysteresis and configurable pullup device on all input pins;
configurable slew rate and drive strength on all output pins
• Package Options
– 14mm × 14mm 80-pin LQFP, 10 mm × 10 mm 64-pin LQFP
© Freescale Semiconductor, Inc., 2009. All rights reserved.
1 page  
2 Pin Assignments
This section shows the pin assignments for the This section shows the pin assignments for the
MC9S08LL64 series devices.
PTE1/LCD14
PTE0/LCD13
PTD7/LCD7
PTD6/LCD6
PTD5/LCD5
PTD4/LCD4
PTD3/LCD3
PTD2/LCD2
PTD1/LCD1
PTD0/LCD0
VCAP1
VCAP2
VLL1
VLL2
VLL3
VLCD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64-Pin LQFP
48 LCD38
47 LCD39
46 LCD40
45 LCD41
44 PTA5/KBIP5/ADP9/LCD42
43 PTA4/KBIP4/ADP8/LCD43
42 PTA3/KBIP3/SCL/MOSI/ADP7
41 PTA2/KBIP2/SDA/MISO/ADP6
40 PTA1/KBIP1/SPSCK/ADP5
39 PTA0/KBIP0/SS/ADP4
38 PTC7/IRQ/TCLK
37 PTC6/ACMPO/BKGD/MS
36 PTC5/TPM2CH1
35 PTC4/TPM2CH0
34 PTC3/TPM1CH1
33 PTC2/TPM1CH0
www.DataSheet4U.com
Figure 2. 64-Pin LQFP
Freescale Semiconductor
MC9S08LL64 Series MCU Data Sheet, Rev. 4
5
5 Page 
ESD Protection and Latch-Up Immunity
where:
TJ = TA + (PD × θJA)
Eqn. 1
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:
PD = K ÷ (TJ + 273°C)
Solving Equation 1 and Equation 2 for K gives:
Eqn. 2
K = PD × (TA + 273°C) + θJA × (PD)2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of TA.
3.5 ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification, ESD stresses were performed for the human body
www.DamtaoSdheeelt4(UH.cBomM), the machine model (MM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless instructed otherwise in the device
specification.
Table 6. ESD and Latch-up Test Conditions
Model
Description
Series resistance
Human
body model
Storage capacitance
Number of pulses per pin
Charge
device
model
Series resistance
Storage capacitance
Number of pulses per pin
Symbol
R1
C
—
R1
C
—
Value
1500
100
3
0
200
3
Unit
Ω
pF
Ω
pF
Freescale Semiconductor
MC9S08LL64 Series MCU Data Sheet, Rev. 4
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MC9S08LL36.PDF ] | |
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