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PDF SST32HF402 Data sheet ( Hoja de datos )
| Número de pieza | SST32HF402 | |
| Descripción | (SST32HFxxx) Multi-Purpose Flash (MPF) SRAM ComboMemory | |
| Fabricantes | Silicon Storage Technology | |
| Logotipo |  |
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Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
SST32HF201 / 202 / 401 / 4022Mb Flash + 1Mb SRAM, 2Mb Flash + 2Mb SRAM,
4Mb Flash + 1Mb SRAM, 4Mb Flash + 2Mb SRAM (x16) MCP ComboMemories
FEATURES:
Preliminary Specifications
• MPF + SRAM ComboMemory
– SST32HF201: 128K x16 Flash + 64K x16 SRAM
– SST32HF202: 128K x16 Flash + 128K x16 SRAM
– SST32HF401: 256K x16 Flash + 64K x16 SRAM
– SST32HF402: 256K x16 Flash + 128K x16 SRAM
• Single 2.7-3.3V Read and Write Operations
• Concurrent Operation
– Read from or write to SRAM while
Erase/Program Flash
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 15 mA (typical) for
Flash or SRAM Read
– Standby Current: 20 µA (typical)
• Flexible Erase Capability
– Uniform 2 KWord sectors
– Uniform 32 KWord size blocks
• Fast Read Access Times:
– Flash: 70 and 90 ns
– SRAM: 70 and 90 ns
• Latched Address and Data for Flash
• Flash Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time:
SST32HF201/202: 2 seconds (typical)
SST32HF401/402: 4 seconds (typical)
• Flash Automatic Erase and Program Timing
– Internal VPP Generation
• Flash End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Conforms to Flash pinout
• Package Available
– 48-ball LFBGA (6mm x 8mm)
PRODUCT DESCRIPTION
The SST32HF20x/40x ComboMemory devices integrate a
128K x16 or 256K x16 CMOS flash memory bank with a
64K x16 or 128K x16 CMOS SRAM memory bank in a
www.DaMtauSlthi-eCeht4ipU.Pcoamckage (MCP), manufactured with SST’s pro-
prietary, high performance SuperFlash technology.
Featuring high performance Word-Program, the flash
memory bank provides a maximum Word-Program time of
14 µsec. The entire flash memory bank can be erased and
programmed word-by-word in typically 2 seconds for the
SST32HF201/202 and 4 seconds for the SST32HF401/
402, when using interface features such as Toggle Bit or
Data# Polling to indicate the completion of Program opera-
tion. To protect against inadvertent flash write, the
SST32HF20x/40x devices contain on-chip hardware and
software data protection schemes.The SST32HF20x/40x
devices offer a guaranteed endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.
The SST32HF20x/40x devices consist of two independent
memory banks with respective bank enable signals. The
Flash and SRAM memory banks are superimposed in the
same memory address space. Both memory banks share
common address lines, data lines, WE# and OE#. The
memory bank selection is done by memory bank enable
signals. The SRAM bank enable signal, BES# selects the
SRAM bank. The flash memory bank enable signal, BEF#
selects the flash memory bank. The WE# signal has to be
used with Software Data Protection (SDP) command
sequence when controlling the Erase and Program opera-
tions in the flash memory bank. The SDP command
sequence protects the data stored in the flash memory
bank from accidental alteration.
The SST32HF20x/40x provide the added functionality of
being able to simultaneously read from or write to the
SRAM bank while erasing or programming in the flash
memory bank. The SRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Word-Program concurrently. All
flash memory Erase and Program operations will automati-
cally latch the input address and data signals and complete
the operation in background without further input stimulus
requirement. Once the internally controlled Erase or Pro-
gram cycle in the flash bank has commenced, the SRAM
bank can be accessed for Read or Write.
The SST32HF20x/40x devices are suited for applications
that use both flash memory and SRAM memory to store
code or data. For systems requiring low power and small
form factor, the SST32HF20x/40x devices significantly
improve performance and reliability, while lowering power
©2001 Silicon Storage Technology, Inc.
S71209-00-000 9/01
557
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
1 page  
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
device. Additionally, a low frequency 4.7 µF electrolytic
capacitor from VDD to VSS should be placed within 1 cm of
the VDD pin.
FUNCTIONAL BLOCK DIAGRAM
Address Buffers
SRAM
AMS-A0
UBS#
LBS#
BES#
BEF#
OE#
WE#
Control Logic
I/O Buffers
DQ15 - DQ8
DQ7 - DQ0
Address Buffers
& Latches
SuperFlash
Memory
557 ILL B1.0
TOP VIEW (balls facing down)
www.DataSheet4U.com
6
A13
5
A9
4
WE#
3
BES#
2
A7
1
A3
SST32HF201/202
A12 A14 A15 A16 USB# DQ15 VSS
A8 A10 A11 DQ7 DQ14 DQ13 DQ6
NC LBS# NC DQ5 DQ12 VDD DQ4
NC NC NC DQ2 DQ10 DQ11 DQ3
NC A6 A5 DQ0 DQ8 DQ9 DQ1
A4 A2 A1 A0 BEF# OE# VSS
ABCDEFGH
TOP VIEW (balls facing down)
SST32HF401/402
6
A13 A12 A14 A15 A16 USB# DQ15 VSS
5
A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6
4
WE# NC LBS# NC DQ5 DQ12 VDD DQ4
3
BES# NC NC NC DQ2 DQ10 DQ11 DQ3
2
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
1
A3 A4 A2 A1 A0 BEF# OE# VSS
ABCDEFGH
FIGURE 1: PIN ASSIGNMENTS FOR 48-BALL LFBGA
©2001 Silicon Storage Technology, Inc.
5
S71209-00-000 9/01 557
5 Page 
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
ADDRESSES AMSS-0
BES#
OE#
UBS#, LBS#
DQ15-0
TRCS
TAAS
TBES
TBLZS
TOES
TOLZS
TBYES
TBYLZS
TOHS
TBHZS
TOHZS
TBYHZS
DATA VALID
Note: WE# remains High (VIH) for the Read cycle
AMSS = Most Significant SRAM Address
FIGURE 2: SRAM READ CYCLE TIMING DIAGRAM
557 ILL F02.0
ADDRESSES AMSS-0
www.DataSheet4U.com
WE#
BES#
TWCS
TASTS
TWPS
TBWS
TAWS
TWRS
UBS#, LBS#
DQ15-8, DQ7-0
TBYWS
TODWS
NOTE 2
TDSS
TOEWS
TDHS
VALID DATA IN
NOTE 2
557 ILL F03.1
FIGURE
Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. If BES# goes Low coincident with or after WE# goes Low, the output will remain at high impedance.
If BES# goes High coincident with or before WE# goes High, the output will remain at high impedance.
Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1
©2001 Silicon Storage Technology, Inc.
11
S71209-00-000 9/01 557
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet SST32HF402.PDF ] | |
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