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PDF CYII4SM014KAA-GEC Data sheet ( Hoja de datos )
| Número de pieza | CYII4SM014KAA-GEC | |
| Descripción | 14Megapixel CMOS Image Sensor | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CYII4SC014KAA-GTC
CYII4SM014KAA-GEC
IBIS4-14000 14Megapixel CMOS Image Sensor
Table 1. Key Performance Parameters
Parameter
Active Pixels
Pixel Size
Optical format
Shutter Type
Master Clock
Frame rate
Sensitivity (@ 650 nm)
Full Well Charge
kTC Noise
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Dynamic Range
Supply Voltage
Power Consumption
Color Filter Array
Packaging
Typical Value
3048 (H) x 4560 (V)
8 µm x 8 µm
35 mm
Rolling Shutter
15 MHz
3 fps at full resolution
1256 V.m2/W.s
65.000 e-
35 e-
223 e-/s
65.4 dB
3.3V
< 176 mW
Mono and RGB
49-pins PGA
Features
The IBIS4-14000 is a CMOS active pixel image sensor that is
comprised of 14 MegaPixels with 3048 x 4560 active pixels on
an 8m pitch. The sensor has a focal plane array of 36 x 24mm2
and operates in rolling shutter mode. At 15 MHz, 3 fps are
achieved at full resolution. On-chip FPN correction is available
The pixel design is based on the high-fill-factor active pixel
sensor technology of Cypress Semiconductor Corporation
(US patent No. 6,225,670 and others). The sensor is available
in a monochrome version and a Bayer (RGB) patterned color
filter array.
This data sheet allows the user to develop a camera system
based on the described timing and interfacing.
Applications
• Digital photography
• Document scanning
• Biometrics
Cypress Semiconductor Corporation
Document #: 38-05709 Rev. *B
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised January 8, 2007
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CYII4SC014KAA-GTC
CYII4SM014KAA-GEC
• Coupling: the IBIS4-14000 can be DC- or AC-coupled to the
AD converter.
Output Amplifier Crossbar Switch (multiplexer)
A crossbar switch is available that routes the green pixels
always to the same output (this is useful for a color device to
avoid gain and offset differences between green pixels). The
switch can be controlled automatically (with a toggle on every
CLK_Y rising edge) or manually (through the SPI register).
Figure 6 shows how it works. A pulse on SYNC_Y resets the
crossbar switch. The initial state after reset of the switchboard
is read from the SPI control register. When the automatic
toggling of the switchboard is enabled, it toggles on every
rising edge of the CLK_Y clock. Separate pins are used for the
SYNC_Y and CLK_Y signals on the crossbar logic these pins
can be connected to the SYNC_YL and CLK_YL pins of the
shift register that is used for readout.
.
Figure 6. Output Amplifier Crossbar Switch
CLK_YR
SYNC_YR
Manual
Q
Power
Power
Power
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Power
Document #: 38-05709 Rev. *B
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CYII4SC014KAA-GTC
CYII4SM014KAA-GEC
SYNC_YR is pulsed for the electronic shutter at the appro-
priate moment.
This timing assumes that the registers that control the
subsampling modes have been loaded in advance (through
the SPI interface), before the pulse on SYNC_YL or
SYNC_YR.
The second reset pulse and the pulses on SYL and SYR (all
pulses drawn in red) are only applied when the rolling
electronic shutter is used. For full frame integration, these
pulses are skipped.
The SYNC_Y pulse is also used to initialize the switchboard
(output multiplexer). This is also done by a synchronous reset
on the rising edge of CLK_Y. Normally the switchboard is
controlled by the shift register used for readout (this is the YL
shift register). This means that pin SYNC_Y can be connected
to SYNC_YL, and pin CLK_Y can be connected to CLK_YL.
The additional RESET BLACK pulse (indicated in dashed lines
in Figure 10 on page 10) can be given to make one or more
lines black. This can be useful to generate a dark reference
signal.
Timing Pulse Pattern for Readout of a Pixel
Figure 11 shows the timing diagram to preset (sync) the X shift
register, read out the image row, and analog-digital
conversion. There are 3 tasks:
• Preset the X shift register: apply a low level to SYNC_X
during a rising edge on CLK_X at the start of a new row
• Readout of the image row: pulse CLK_X
• Analog-digital conversion: clock the ADC
The SYNC pulses perform a synchronous reset of the shift
registers to the first row/column on a rising edge on CLK. This
is identical for all shift registers (YR, YL and X).
Note The SYNC_X signal has a set-up time Ts of 150 ns. For
the YR and YS shift registers, the set-up time is 200 ns. CLK_X
must be stable at least during this set-up time.
In the case where a partial row readout has been performed,
2 CLK_X pulses (with SYNC_X = LOW) are required to fully
deselect the column where the X pointer has been stopped. A
single CLK_X will leave the column partially selected, which
will then have a different response when read out in the next
row. When full row readout has been performed, the last
column will be fully deselected by a single CLK_X pulse (with
SYNC_X = LOW). The X-register is reset by a single CLK_X
pulse (with SYNC_X = LOW). In case of partial row readout,
the SYNC_X pulse has to be given before the sample pulses
(SHR and SHS) of the row sampling process, in order to avoid
a different response of the last column of the previous window.
For the X shift register, the analog signal is delayed by 2 clock
periods before it becomes available at the output (due to
internal processing of the signal in the columns and output
amplifier). The figure gives an example of an ADC clock for an
ADC that samples on the rising edge.
Fast Frame Reset Timing Diagram
Figure 12 on page 12 shows the reset timing for a fast frame
reset.
SYL and SYR can be kept both high to make the reset
mechanism faster and reduce propagation delays. PC, SHS,
SHR can be kept high since they don’t interact with the pixel
reset mechanism.
Table 5 on page 12 lists timing specifications for RESET,
CLK_Y and SELECT.
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Figure 11. Row Readout Timing Sequence
Ts Ts
SYNC_X
CLK_X
A n a lo g
O utput
CLK_ADC
(exam ple)
X
pixel 1 pixel 2 pixel 3
Document #: 38-05709 Rev. *B
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