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PDF HT82A851R Data sheet ( Hoja de datos )
| Número de pieza | HT82A851R | |
| Descripción | USB Audio MCU | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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HT82A851R
USB Audio MCU
Features
· Operating voltage: fSYS = 6M/12MHz: 3.3V~5.5V
· 16 bidirectional I/O lines (max.)
· Two 16-bit programmable timer/event counters and
overflow interrupts
· 4096´15 program memory ROM
· 384´8 data memory RAM (Bank0,1)
· USB 2.0 full speed compatible
· USB spec V1.1 full speed operation and USB audio
device class spec V1.0
· Built-in digital PGA (Programmable Gain Amplifier)
· 48kHz/8kHz sampling rate for audio playback
controlled by software option
· 8kHz audio recording sampling rate
· Supports audio playback digital volume control
· 5 endpoints supported (endpoint 0 included)
· Supports 1 Control, 2 Interrupt, 2 Isochronous
transfer
· Two hardware implemented Isochronous transfers
· Total FIFO size: 464 bytes
(8, 8, 384, 32, 32 for EP0~EP4)
· Programmable frequency divider (PFD)
· Integrated SPI hardware circuit
· Play/Record Interrupt
· HALT and wake-up features reduce power
consumption
· Watchdog Timer
· 16-level subroutine nesting
· Bit manipulation instruction
· 15-bit table read instruction
· 63 powerful instructions
· All instructions executed within one or two machine
cycles
· Low voltage reset function (3.0V±0.3V)
· 24-pin SSOP package
General Description
The HT82A851R is an 8-bit high performance RISC-like
microcontroller designed for wireless USB Phone prod-
uct applications. The HT82A851R combines a SPI,
USB transceiver, SIE (Serial Interface Engine), audio
class processing unit, FIFO and an 8-bit MCU into a sin-
gle chip. The play frequency in the HT82A851R oper-
ates at a sampling rate of 48/8kHz. HT82A851R has a
digital programmable gain amplifier. The gain range is
from -32dB to +6dB. For the Isochronous input, the digi-
tal gain range is from 0dB to 19.5dB.
www.DataSheet4U.com
Rev. 1.20
1 June 15, 2007
1 page  
HT82A851R
Functional Description
Execution Flow
The microcontroller system clock is sourced from a
crystal oscillator. The system clock is internally divided
into four non-overlapping clocks. One instruction cycle
consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while
decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each
instruction to be effectively executed in a cycle. If an
instruction changes the program counter, two cycles are
required to complete the instruction.
Program Counter - PC
The program counter, PC, controls the sequence in
which the instructions stored in the program memory are
executed. Its contents specify the full program memory
range.
After accessing a program memory word to fetch an
instruction code, the contents of the program counter
are incremented by one. The program counter then
points to the memory word containing the next
instruction code.
When executing a jump instruction, a conditional skip
execution, loading to the PCL register, performing a
subroutine call or returning from a subroutine, an initial
reset, an internal interrupt, external interrupt or return
from interrupts, the PC manipulates the program
transfer by loading the address corresponding to each
instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise the next instruction is executed.
The lower byte of the program counter, PCL, is a
readable and writeable register. Moving data into the
PCL performs a short jump. The destination will be
within the current program memory page.
When a control transfer takes place, an additional
dummy cycle is required.
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
S y s te m C lo c k
O S C 2 ( R C o n ly )
PC PC
PC +1 PC +2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
Execution Flow
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
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Mode
Program Counter
*11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
Initial Reset
000000000000
Reserved
000000000100
Timer/Event Counter 0 Overflow 0 0 0 0 0 0 0 0 1 0 0 0
Timer/Event Counter 1 Overflow 0 0 0 0 0 0 0 0 1 1 0 0
Play Interrupt
000000010000
Serial Interface Interrupt
000000010100
Record Interrupt
000000011000
Skip
Program Counter+2
Loading PCL
*11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch
#11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from Subroutine
S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Program Counter
Note: *11~*0: Program counter bits
#11~#0: Instruction code bits
S11~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.20
5 June 15, 2007
5 Page 
HT82A851R
Bit No.
0
1
2
3~7
Label
WS0
WS1
WS2
¾
Function
Watchdog Timer division ratio selection bits
Bit 2,1,0 = 000, Division Ratio = 1:1
Bit 2,1,0 = 001, Division Ratio = 1:2
Bit 2,1,0 = 010, Division Ratio = 1:4
Bit 2,1,0 = 011, Division Ratio = 1:8
Bit 2,1,0 = 100, Division Ratio = 1:16
Bit 2,1,0 = 101, Division Ratio = 1:32
Bit 2,1,0 = 110, Division Ratio = 1:64
Bit 2,1,0 = 111, Division Ratio = 1:128
Unused bit, read as ²0²
WDTS (09H) Register
W DT O SC
S y s te m C lo c k /4
M ask
O p tio n
S e le c t
8 - b it C o u n te r
W S 0~W S 2
W D T P r e s c a le r
7 - b it C o u n te r
8 -to -1 M U X
Watchdog Timer
W D T T im e - o u t
If the instruction clock is selected as the WDT clock
source, the WDT operates in the same manner except in
the halt mode. In the HALT mode, the WDT stops count-
ing and lose its protecting purpose. In this situation the
logic can only be re-started by external logic. The high
nibble of the WDTS is reserved for the DAC write mode.
The WDT overflow under normal operation initializes a
²chip reset² and sets the status bit ²TO². In the HALT
mode, the overflow initializes a ²warm reset², and only
the program counter and stack pointer are reset to zero.
To clear the contents of the WDT, there are three meth-
ods to be adopted, i.e., an external reset (a low level to
RESET), a software instruction, and a ²HALT² instruc-
tion. There are two types of software instructions; ²CLR
WDT² and the other set ²CLR WDT1² and ²CLR
www.DataSheet4UW.cDoTm2². Of these two types of instruction, only one type
of instruction can be active at a time depending on the
configuration option ²CLR WDT² times selection option.
If the ²CLR WDT² is selected (i.e., CLR WDT times
equal one), any execution of the ²CLR WDT² instruction
clears the WDT. In the case that ²CLR WDT1² and ²CLR
WDT2² are chosen (i.e., CLR WDT times equal two),
these two instructions have to be executed to clear the
WDT; otherwise, the WDT may reset the chip due to a
time-out.
Power Down Operation - HALT
The Power-down mode is entered by the execution of a
²HALT² instruction and results in the following:
· The system oscillator will be turned off but the WDT
oscillator keeps running if the internal WDT oscillator
is selected.
· The contents of the on-chip data memory and regis-
ters remain unchanged.
· The WDT and WDT prescaler will be cleared and will
start counting again if the WDT clock is sourced from
the internal WDT oscillator.
· All of the I/O ports remain in their original condition.
· The PDF flag is set and the TO flag is cleared.
The system can leave the Power-down mode by means
of an external reset, an interrupt, an external falling
edge signal on port A or a WDT overflow. An external
reset causes a device initialisation and the WDT
overflow performs a ²warm reset². After the TO and PDF
flags are examined, the cause for the device reset can
be determined. The PDF flag is cleared by a system
power-up or by executing the ²CLR WDT² instruction
and is set when executing the ²HALT² instruction. The
TO flag is set if the WDT time-out occurs, and causes a
wake-up that only resets the program counter and SP;
the others remain in their original status.
A port A wake-up and interrupt methods can be
considered as a continuation of normal execution. Each
pin in port A can be independently selected to wake-up
the device using configuration options. After awakening
from an I/O port stimulus, the program will resume
execution at the next instruction. If the device is
awakened from an interrupt, two sequence may occur. If
the related interrupt is disabled or the interrupt is
enabled but the stack is full, the program will resume
execution at the next instruction. If the interrupt is
enabled and the stack is not full, the regular interrupt
response takes place. If an interrupt request flag is set to
²1² before entering the Power-down mode, the wake-up
function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 tSYS (system clock
periods) to resume normal operation, i.e., a dummy
period is inserted. If the wake-up results from an
Rev. 1.20
11 June 15, 2007
11 Page | ||
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| PDF Descargar | [ Datasheet HT82A851R.PDF ] | |
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