|
|
Número de pieza | CY7C1165V18 | |
Descripción | (CY7C11xxV18) SRAM 4-Word Burst Architecture | |
Fabricantes | Cypress Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de CY7C1165V18 (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
No Preview Available ! CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
18-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency)
Features
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 300 MHz to 400 MHz clock for high bandwidth
■ 4-word burst to reduce address bus frequency
■ Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 800 MHz) at 400 MHz
■ Read latency of 2.5 clock cycles
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate port selects for depth expansion
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ Available in x8, x9, x18, and x36 configurations
■ Full data coherency providing most current data
■ Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD[1]
■ Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ Variable drive HSTL output buffers
www■.DJaTtaASGhe1e1t44U9..c1ocmompatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
Configurations
With cycle read latency of 2.5 cycles:
CY7C1161V18 – 2M x 8
CY7C1176V18 – 2M x 9
CY7C1163V18 – 1M x 18
CY7C1165V18 – 512K x 36
Functional Description
The CY7C1161V18, CY7C1176V18, CY7C1163V18, and
CY7C1165V18 are 1.8V Synchronous Pipelined SRAMs
equipped with QDR™-II+ architecture. QDR-II+ architecture
consists of two separate ports to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR-II+ architecture has separate data inputs and
data outputs to completely eliminate the need to turn around the
data bus that is required with common IO devices. Each port can
be accessed through a common address bus. Addresses for
read and write addresses are latched onto alternate rising edges
of the input (K) clock. Accesses to the QDR-II+ read and write
ports are completely independent of one another. In order to
maximize data throughput, both read and write ports are
equipped with Double Data Rate (DDR) interfaces. Each
address location is associated with four 8-bit words
(CY7C1161V18), 9-bit words (CY7C1176V18), 18-bit words
(CY7C1163V18), or 36-bit words (CY7C1165V18) that burst
sequentially into or out of the device. Because data can be trans-
ferred into and out of the device on every rising edge of both input
clocks K and K, memory bandwidth is maximized while simpli-
fying system design by eliminating bus turnarounds.
Depth expansion is accomplished with port selects for each port.
Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the or K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
400 MHz
400
1080
375 MHz
375
1020
333 MHz
333
920
300 MHz
300
850
Unit
MHz
mA
Note
1.
The QDR consortium
= 1.4V to VDD.
specification
for
VDDQ
is
1.5V
+
0.1V.
The
Cypress
QDR
devices
exceed
the
QDR
consortium
specification
and
are
capable
of
supporting
VDDQ
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-06582 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 15, 2007
[+] Feedback
1 page CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
Pin Configurations (continued)
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1163V18 (1M x 18)
1 2 3 4 56 7 8
A CQ NC/144M NC/36M WPS BWS1 K NC/288M RPS
B NC Q9 D9 A
NC
K
BWS0
A
C NC
NC D10 VSS
A
NC
A VSS
D
NC
D11 Q10 VSS
VSS
VSS
VSS
VSS
E NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
M
NC
NC
D16 VSS
VSS
VSS
VSS
VSS
N NC D17 Q16 VSS
A
A
A VSS
P NC NC Q17 A
A QVLD A
A
R
TDO
TCK
A
A
A NC A
A
9
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
10
NC/72M
NC
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
1
A CQ
www.DataShBeet4U.coQm27
C D27
D D28
E Q29
F Q30
G D30
H DOFF
J D31
K Q32
L Q33
M D33
N D34
P Q35
R TDO
23
NC/288M NC/72M
Q18 D18
Q28 D19
D20 Q19
D29
Q21
D22
VREF
Q31
D32
Q24
Q34
D26
D35
Q20
D21
Q22
VDDQ
D23
Q23
D24
D25
Q25
Q26
TCK
A
CY7C1165V18 (512K x 36)
4
WPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
5
BWS2
BWS3
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
A
6
K
K
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
QVLD
NC
7
BWS1
BWS0
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
A
8
RPS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
9 10
NC/36M NC/144M
D17 Q17
D16 Q7
Q16 D15
Q15 D6
D14
Q13
VDDQ
D12
Q14
D13
VREF
Q4
Q12 D3
D11 Q11
D10 Q1
Q10 D9
Q9 D0
A TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Document Number: 001-06582 Rev. *C
Page 5 of 29
[+] Feedback
5 Page CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
Write Cycle Descriptions
The write cycle descriptions of CY7C1161V18 and CY7C1163V18 follow.[3, 11]
BWS0/ BWS1/
NWS0 NWS1
K
K
Comments
L L L–H – During the data portion of a write sequence:
CY7C1161V18 − both nibbles (D[7:0]) are written into the device.
CY7C1163V18 − both bytes (D[17:0]) are written into the device.
L L – L-H During the data portion of a write sequence:
CY7C1161V18 − both nibbles (D[7:0]) are written into the device.
CY7C1163V18 − both bytes (D[17:0]) are written into the device.
L H L–H – During the data portion of a write sequence:
CY7C1161V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1163V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L H – L–H During the data portion of a write sequence:
CY7C1161V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1163V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H L L–H – During the data portion of a write sequence:
CY7C1161V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1163V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H L – L–H During the data portion of a write sequence:
CY7C1161V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1163V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H H L–H – No data is written into the device during this portion of a write operation.
H H – L–H No data is written into the device during this portion of a write operation.
The write cycle operation of CY7C1176V18 follows.[3, 11]
BWS0
K
K
L L–H – During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
www.DatLaSheet4U–.com L–H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
H L–H – No data is written into the device during this portion of a write operation.
H – L–H No data is written into the device during this portion of a write operation.
Note
11. Is based upon a Write cycle was initiated per the Write Cycle Description Truth Table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different
portions of a Write cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-06582 Rev. *C
Page 11 of 29
[+] Feedback
11 Page |
Páginas | Total 29 Páginas | |
PDF Descargar | [ Datasheet CY7C1165V18.PDF ] |
Número de pieza | Descripción | Fabricantes |
CY7C1165V18 | (CY7C11xxV18) SRAM 4-Word Burst Architecture | Cypress Semiconductor |
Número de pieza | Descripción | Fabricantes |
SLA6805M | High Voltage 3 phase Motor Driver IC. |
Sanken |
SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |