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PDF LTC4224-2 Data sheet ( Hoja de datos )
| Número de pieza | LTC4224-2 | |
| Descripción | Compact Dual Low Voltage Hot Swap Controller | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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www.DataSheet4U.com
LTC4224-1/LTC4224-2
Compact Dual Low
Voltage Hot Swap Controller
FEATURES
n Allows Safe Board Insertion and Removal from a
Live Backplane
n Controls Load Voltages from 1V to 6V
n No Gate Components Required
n Adjustable Current Limit with Circuit Breaker
n Limits Peak Fault Current in ≤1μs
n No External Timing Capacitor Required
n Adjustable Supply Voltage Power-Up Rate
n Gate Drive for External N-channel MOSFET
n LTC4224-1: Latchoff After Fault
n LTC4224-2: Automatic Retry After Fault
n 10-Lead MSOP and 3mm × 2mm DFN Packages
APPLICATIONS
n Optical Networking
n Low Voltage Hot Swap
n Electronic Circuit Breakers
DESCRIPTION
The LTC®4224 Dual Low Voltage Hot Swap™ controller
allows a board to be safely inserted and removed from a
live backplane. It controls two supplies with external N-
channel MOSFETs and operates with one supply as low
as 1V provided the other supply is 2.7V or greater. The
LTC4224 can ramp up the supplies in any order and at
adjustable ramp rates. To minimize the number of external
components and PCB area, the gate capacitor is optional,
all timing delays are generated internally, and the ON pins
have integrated pull-up currents.
Protection against overcurrent faults is provided by a fast-
acting current limit and timed circuit breakers. A FAULT pin
signals overcurrent faults. The LTC4224-1 remains off after
a fault, while the LTC4224-2 automatically tries to apply
power again after a four second cool-down period.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
TYPICAL APPLICATION
0.015Ω
5V
3.3V
FDS6911
0.010Ω
5V
1A
3.3V
2A
VCC1 SENSE1 VCC2 SENSE2 GATE1 GATE2
FAULT
LTC4224
LTC4224
ON1
ON2
GND
GND
CONNECTOR PLUG-IN
CARD
422412 TA01a
Normal Power-Up Waveform
VOUT1
5V/DIV
VOUT2
5V/DIV
IIN1
2A/DIV
IIN2
2A/DIV
0.5ms/DIV
CLOAD = 150μF
422412 TA01b
422412fa
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LTC4224-1/LTC4224-2
PIN FUNCTIONS
SENSE1, SENSE2 (Pins 1,10): Current Sense Input. Con-
nect this pin to an external sense resistor. The current limit
circuit controls GATEn to limit the voltage between VCCn
and SENSEn to 25mV. An Electronic Circuit Breaker (ECB)
is active during current limiting and trips after 5ms. To
disable current limit, connect this pin to VCCn.
VCC1, VCC2 (Pins 2, 9): Supply Voltage and Current Sense
Input. An undervoltage lockout circuit disables the part
until VCC, the higher of VCC1 and VCC2, exceeds 2.4V. The
lower supply is disabled until it exceeds 0.8V.
GATE1, GATE2 (Pins 3, 8): Gate Drive for External N-channel
MOSFET. A charge pump sources 10μA from GATE to turn
on the external MOSFET. An internal clamp limits the gate
voltage to 5.5V above the higher of VCC1 and VCC2. During
turn-off, a 1.5mA pulldown current discharges GATE to
ground. During short-circuits, a 125mA pulldown current
is activated to discharge GATE to ground.
FAULT (Pin 4): Fault Status Output. Open-drain output
that is normally pulled high to VCC1 or VCC2 by an exter-
nal resistor. It is pulled low when the ECB trips due to an
overcurrent condition at either supply. This pin may be
left open if unused.
ON1, ON2 (Pins 5, 6): On Control Input. A falling edge
turns on the external N-channel MOSFET and a rising edge
turns it off. A low to high transition on this pin resets an
ECB fault for the corresponding channel. Internally pulled
up to VCC by a 10μA current source.
GND (Pin 7): Device Ground.
Exposed Pad (DFN Package Only): Exposed Pad may be
left open or connected to device ground.
FUNCTIONAL DIAGRAM
SENSE1
– ACL1
VCC1
25mV
+
+
0.8V –
VCC
+
2.4V –
+
0.8V –
VCC2
25mV
ACL2
+
–
SENSE2
CHARGE
PUMP
10μA
5.5V
VCC
GATE1
ECB1
GATE
PULLDOWN
VCC
10μA
ON1 +
ON1
VCC1 UV
VCC2 UV
ECB2
LOGIC
CONTROL
– 0.8V
FAULT
VCC
10μA
ON2 +
ON2
CHARGE
PUMP
– 0.8V
10μA
GATE
PULLDOWN
5.5V
VCC
GATE2
GND
422412 FD
422412fa
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LTC4224-1/LTC4224-2
APPLICATIONS INFORMATION
VCC2
1 SENSE2 10
2 VCC2 9
3 GATE2 8
4 GND 7
5 LTC4224 6
Z1
VIAS TO
GND PLANE
RSNUB SNUBBER
CSNUB NETWORK
422412 F11
Figure 11. Recommended Layout for Input
Supply Transient Protection Network
Also, bypass locally with a 10μF electrolytic and 100nF
ceramic, or alternatively clamp the input with a transient
voltage suppressor (Z1) as shown in Figure 10. A 10Ω,
100nF snubber damps the response and eliminates ring-
ing. A recommended layout of the transient protection
devices Z1, RSNUB and CSNUB around the LTC4224 is
shown in Figure 11.
PCB Layout Considerations
For proper operation of the LTC4224’s electronic circuit
breaker, Kelvin connections to the sense resistors are
strongly recommended. The PCB layout should be balanced
and symmetrical to minimize wiring errors. In addition, the
3.3V 5V
R2 R1
10
9
8 11
7
6
1
2
3
4
5
FDS6911
LTC4224
BOTTOM SIDE
TOP SIDE
Figure 12. Recommended Layout for
Power MOSFET and Sense Resistors
422412 F12
PCB layout for the sense resistors and the power MOSFETs
should include good thermal management techniques for
optimal device power dissipation. A recommended PCB
layout for the sense resistors and the power MOSFET
around the LTC4224 is illustrated in Figure 12. Note that
it is important to keep the trace from the LTC4224’s GATE
pin to the FDS6911’s gate short.
In Hot Swap applications where load currents can be 10A,
wide PCB traces are recommended to minimize resistance
and temperature rise. The suggested trace width for 1oz
copper foil is 0.03" for each ampere of DC current to keep
PCB trace resistance, voltage drop and temperature rise to
a minimum. Note that the sheet resistance of 1oz copper
foil is approximately 0.5mΩ/square and voltage drops
due to trace resistances add up quickly in high current
applications.
In most applications, it is necessary to use plated-through
vias to make circuit connections from component layers to
power and ground layers internal to the PCB. For 1oz cop-
per foil plating, a general rule is 1A of DC current per via.
Consult your PCB fabrication facility for design rules
pertaining to other plating thicknesses.
Design Example
As a design example, consider the following specifications:
VCC1 = 5V, VCC2 = 3.3V, ILOAD1(MAX) = 1A, ILOAD2(MAX) = 2A,
CLOAD1 = CLOAD2 = 150μF (see Figure 1).
First, select the sense resistor for each supply. Calculate
the R1 and R2 values based on the maximum load cur-
rent and the minimum circuit breaker threshold limit,
ΔVSENSE(CB)(MIN).
If a 1% tolerance is assumed for the sense resistors, then
the following values of resistance should suffice:
Table 2. Sense Resistor Values
SUPPLY VOLTAGE RSENSE (1%)
5V 15mΩ
3.3V 10mΩ
ITRIP(MIN)
1.49A
2.23A
ITRIP(MAX)
1.85A
2.78A
For proper operation, ITRIP(MIN) must exceed the maxi-
mum load current with margin, so RSENSE1 = 15mΩ and
RSENSE2 = 10mΩ should suffice for the VCC1 and VCC2
supplies respectively.
422412fa
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11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LTC4224-2.PDF ] | |
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