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PDF LTC4264 Data sheet ( Hoja de datos )

Número de pieza LTC4264
Descripción High Power PD Interface Controller
Fabricantes Linear Technology 
Logotipo Linear Technology Logotipo



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FEATURES
Complete High Power PD Interface Controller
IEEE 802.3af® Compliant
Onboard 750mA Power MOSFET
Complementary Power Good Outputs
Flexible Auxiliary Power Options
Precision Dual Current Limit with Disable
Programmable Classification Current to 75mA
Onboard 25k Signature Resistor with Disable
Undervoltage Lockout
Complete Thermal Overload Protection
Available in Low Profile (4mm × 3mm) DFN Package
APPLICATIONS
802.11n Access Points
High Power VoIP Video Phones
RFID Reader Systems
PTZ Security Cameras and Surveillance Equipment
LTC4264
High Power PD Interface
Controller with 750mA
Current Limit
DESCRIPTION
The LTC®4264 is an integrated Powered Device (PD) in-
terface controller intended for IEEE 802.3af Power over
Ethernet (PoE) and high power PoE applications up to 35W.
By including a precision dual current limit, the LTC4264
keeps inrush below the IEEE802.3af current limit levels
to ensure interoperability success while allowing for high
power PD operation. The LTC4264 includes a field-proven
power MOSFET delivering up to 750mA to the PD load while
maintaining compliance with the IEEE802.3af standard.
Complementary power good outputs allow the LTC4264 to
interface directly with a host of DC/DC converter products.
The LTC4264 provides a complete signature and power
interface solution for PD designs by incorporating the 25k
signature resistor, classification circuitry, input current
limit, undervoltage lockout, thermal overload protection,
signature disable and power good signaling.
The LTC4264 PD interface controller can be used along with
a variety of Linear Technology DC/DC converter products
to provide a complete, cost effective power solution for
high power PD applications.
The LTC4264 is available in the space-saving low profile
(4mm × 3mm) DFN package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
–54V FROM
DATA PAIR
~+
DF1501S
~–
0.1µF
–54V FROM
SPARE PAIR
~+
DF1501S
~–
SMAJ58A
RCLASS
LTC4264
SHDN
GND
RCLASS PWRGD
PWRGD
ILIM_EN
VIN
VOUT
5µF +
MIN
VIN
SWITCHING
POWER
SUPPLY
RUN
RTN
+
3.3V
TO LOGIC
4264 TA01a
VIN
50V/DIV
VOUT
50V/DIV
PWRGD – VOUT
50V/DIV
IIN
200mA/DIV
Turn On vs Time
CLOAD = 100µF
TIME (5ms/DIV)
4264 TA01b
4264f
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LTC4264
PIN FUNCTIONS
SHDN (Pin 1): Shutdown Input. Used to command the
LTC4264 to present an invalid signature. Connecting
SHDN to GND lowers the signature resistance to an invalid
value and disables other LTC4264 operations. If unused,
tie SHDN to VIN.
NC (Pin 2): No Internal Connection.
RCLASS (Pin 3): Class Select Input. Used to set the current
the LTC4264 maintains during classification. Connect a
resistor between RCLASS and VIN. (See Table 2.)
ILIM_EN (Pin 4): Input Current Limit Enable. Used to control
LTC4264 current limit behavior during powered operation.
For normal operation, float ILIM_EN to enable ILIMIT_HIGH
current. Tie ILIM_EN to VIN to disable input current limit.
Note that the inrush current limit does not change with
ILIM_EN selection. See Applications Information.
VIN (Pins 5, 6): Power Input. Tie to the PD input through
the diode bridge. Pins 5 and 6 must be electrically tied
together.
VOUT (Pins 7, 8): Power Output. Supplies power to the
PD load through the internal power MOSFET. VOUT is high
impedance until the input voltage rises above the UVLO
turn-on threshold. The output is then connected to VIN
through a current-limited internal MOSFET switch. Pins 7
and 8 must be electrically tied together.
PWRGD (Pin 9): Active High Power Good Output, Open
Collector. Signals to the DC/DC converter that the LTC4264
MOSFET is on and that the converter can start operation.
High impedance indicates power is good. PWRGD is ref-
erenced to VOUT and is low impedance during inrush and
in the event of a thermal overload. PWRGD is clamped
14V above VOUT.
PWRGD (Pin 10): Active Low Power Good Output, Open-
Drain. Signals to the DC/DC converter that the LTC4264
MOSFET is on and that the converter can start operation.
Low impedance indicates power is good. PWRGD is
referenced to VIN and is high impedance during detec-
tion, classification and in the event of a thermal overload.
PWRGD has no internal clamps.
NC (Pin11): No Internal Connection.
GND (Pin 12): Ground. Tie to system ground and power
return through the input diode bridge.
Exposed Pad (Pin 13): Must be soldered to electrically
isolated heat sink.
4264f
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LTC4264
APPLICATIONS INFORMATION
During classification, the PSE presents a fixed voltage
between –15.5V and –20.5V to the PD (Figure 6). With
the input voltage in this range, the LTC4264 asserts a load
current from the GND pin through the RCLASS resistor. The
magnitude of the load current is set with the selection of
the RCLASS resistor. The resistor value associated with
each class is shown in Table 2.
Table 2. Summary of IEEE 802.3af Power Classifications and
LTC4264 RCLASS Resistor Selection
CLASS
USAGE
MAXIMUM
POWER LEVELS
AT INPUT OF PD
(W)
NOMINAL
CLASSIFICATION
LOAD CURRENT
(mA)
LTC4264
RCLASS
RESISTOR
(Ω, 1%)
0 Default 0.44 to 12.95
<5
Open
1 Optional 0.44 to 3.84
10.5
124
2 Optional 3.84 to 6.49
18.5
69.8
3 Optional 6.49 to 12.95
28
45.3
4 Reserved by IEEE. See Apps
40
30.9
5 Undefined IEEE. See Apps
56
22.1
A substantial amount of power is dissipated in the LTC4264
during classification. The IEEE 802.3af specification limits
the classification time to 75ms in order avoid excessive
heating. The LTC4264 is designed to handle the power
dissipation during the probe period. If the PSE probing
exceeds 75ms, the LTC4264 may overheat. In this situa-
tion, the thermal protection circuit will engage and disable
the classification current source, protecting the LTC4264
from damage. When the die cools, classification is auto-
matically resumed.
Classification presents a challenging stability problem
for the PSE due to the wide range of loads possible. The
LTC4264 has been designed to avoid PSE interoperability
problems by maintaining a positive I-V slope throughout
the signature and classification ranges up to UVLO turn-
on as shown in Figure 6b. The positive I-V slope avoids
areas of negative resistance and helps prevent the PSE
from power cycling or getting “stuck” during signature
or classification probing. In the event a PSE overshoots
beyond the classification voltage range, the available load
current aids in returning the PD back into the classification
voltage range. (The PD input may otherwise be “trapped”
by a reverse-biased diode bridge and the voltage held by
the 0.1µF capacitor.) By gently ramping the classification
current on and maintaining a positive I-V slope until UVLO
turn-on, the LTC4264 provides a well behaved load, as-
suring interoperability with any PSE.
CURRENT PATH
PSE
PROBING
VOLTAGE
SOURCE
–15.5V TO –20.5V
V
PSE CURRENT MONITOR
RCLASS
LTC4264
RCLASS
VIN
GND
4264 F06a
CONSTANT
LOAD
CURRENT
INTERNAL
TO LTC4264
PSE PD
Figure 6a. PSE Probing PD During Classification
0 –10 –20 –30 –40
INPUT VOLTAGE (V)
4264 F06b
Figure 6b. LTC4264 Positive I-V Slope
4264f
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