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PDF LMH0356 Data sheet ( Hoja de datos )

Número de pieza LMH0356
Descripción 3Gbps HD/SD SDI Reclocker
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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No Preview Available ! LMH0356 Hoja de datos, Descripción, Manual

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PRELIMINARY
October 2007
LMH0356
3Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4
EQs
General Description
The LMH0356 3Gbps HD/SD SDI Reclocker with 4:1 Input
Mux and FR4 EQs retimes serial digital video data conforming
to the SMPTE 424M, SMPTE 292M, and SMPTE 259M (C)
standards. The LMH0356 operates at serial data rates of 270
Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps.
The LMH0356 supports DVB-ASI operation at 270 Mbps. The
LMH0356 includes an integrated 4:1 input multiplexer for se-
lecting one of four input data streams for retiming. In addition,
the four inputs of the LMH0356 each have an FR4 equalizer
capable of equalizing 0-30” of FR4 trace length.
The LMH0356 automatically detects the incoming data rate
and adjusts itself to retime the incoming data to suppress ac-
cumulated jitter. The LMH0356 recovers the serial data-rate
clock and optionally provides it as an output. The LMH0356
has two differential serial data outputs; the second output may
be selected as a low-jitter, data-rate clock output. Controls
and indicators are: serial clock or second serial data output
select, manual rate select input, SD/HD rate indicator output,
lock detect output, auto/manual data bypass, output mute,
and device enable. The serial data inputs, outputs, and serial
clock outputs are differential LVPECL compatible. The CML
serial data and serial clock outputs are suitable for driving
100differentially terminated networks. The control logic in-
puts and outputs are LVCMOS compatible.
The LMH0356 is powered from a single 3.3V supply. Power
dissipation is typically 440 mW. The device is housed in a 48-
pin LLP package.
Features
Supports SMPTE 424M, SMPTE 292M, and SMPTE
259M (C) serial digital video standards
Supports 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967
Gbps, and 2.97 Gbps serial data rate operation
Supports DVB-ASI at 270 Mbps
Single 3.3V supply operation
440 mW typical power consumption
Integrated 4:1 multiplexed input
0-30” FR4 equalizer on each multiplexed input
Two differential, reclocked outputs
Choice of second reclocked output or recovered clock
output
Single 27 MHz external crystal or reference clock input
Manual rate select input
SD/HD operating rate indicator output
Lock Detect indicator output
Output mute function for data and clock
Auto/Manual reclocker bypass
Device power down control (10mW typical power
consumption in disabled state)
Differential LVPECL compatible serial data inputs and
outputs
LVCMOS control inputs and indicator outputs
48-Pin LLP package
Industrial temperature range: -40°C to +85°C
Footprint compatible with the LMH0056
Applications
SDTV/HDTV and 3Gbps serial digital video interfaces for:
Digital video routers and switchers
Digital video processing and editing equipment
DVB-ASI equipment
Video standards and format converters
2.97 Gbps Signal Before FR4
Equalization (0.6 UI Jitter)
2.97 Gbps Signal After FR4
Equalization (0.23 UI JItter)
2.97 Gbps Signal After Reclocking
(0.06 UI JItter)
30016710
© 2007 National Semiconductor Corporation 300167
30016711
30016712
www.national.com

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LMH0356 pdf
wwPwi.nDatDaSehesect4Uri.cpomtions
Pin Name
1 SDI0
2 SDI0
3 VCC
4 SDI1
5 SDI1
6 VCC
7 SDI2
8 SDI2
9 ENABLE
10 SDI3
11 SDI3
12 VCC
13 VEE
14 VCC
15 BYPASS/AUTO BYPASS
16 OUTPUT MUTE
17 VEE
18 XTAL IN/EXT CLK
19 VEE
20 VEE
21 VEE
22 XTAL OUT
23 VEE
24 LOCK DETECT
25 VEE
26 VEE
27 VEE
28 SCO/SDO2
29 SCO/SDO2
30 VCC
31 VCC
32 SDO
33 SDO
34 VCC
35 VCC
36 SD/HD
37 SCO_EN
38 VEE
39 VEE
40 VEE
41 VEE
42 VEE
43 LF1
44 LF2
45 RATE 0
46 RATE 1
47 SEL0
Description
Data Input 0 True
Data Input 0 Complement
Positive power supply input
Data Input 1 True
Data Input 1 Complement
Positive power supply input
Data Input 2 True
Data Input 2 Complement
Device Enable
Data Input 3 True
Data Input 3 Complement
Positive power supply input
Negative power supply input
Positive power supply input
Bypass/Auto Bypass mode select
Data and Clock Output Mute input (active low)
Negative power supply input
Crystal or External Oscillator input
Negative power supply input
Negative power supply input
Negative power supply input
Crystal Oscillator output
Negative power supply input
PLL Lock Detect output (active high)
Negative power supply input
Negative power supply input
Negative power supply input
Serial Clock or Serial Data Output 2 Complement
Serial Clock or Serial Data Output 2 True
Positive power supply input
Positive power supply input
Data Output Complement
Data Output True
Positive power supply input
Positive power supply input
Data Rate Range output
Serial Clock or Serial Data 2 Output select (active high enables serial clock output)
Negative power supply input
Negative power supply input
Negative power supply input
Negative power supply input
Negative power supply input
Loop Filter
Loop Filter
Data Rate select input
Data Rate select input
Data Input select input
5 www.national.com

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LMH0356 arduino
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30016709
FIGURE 2. Equivalent SDO Output Circuit (SDO, SDO, SCO/SDO2, SCO/SDO2)
OPERATING SERIAL DATA RATES
This device operates at serial data rates of 270 Mbps, 1483
Mbps, 1485 Mbps, 2967 Mbps, and 2970 Mbps. The device
does not lock to harmonics of these rates. The device does
not lock and automatically enters the reclocker bypass mode
for the following data rates: 143 Mbps, 177 Mbps, 360 Mbps,
and 540 Mbps.
SERIAL DATA CLOCK/SERIAL DATA 2 OUTPUT
The Serial Data Clock/Serial Data 2 Output is controlled by
the SCO_EN input and provides either a second retimed se-
rial data output or a low jitter differential clock output appro-
priate to the serial data rate being processed. When operating
as a serial clock output, the rising edge of the clock will be
positioned within the corresponding serial data bit interval
within 10% of the center of the data interval.
Differential output SCO/SDO2 functions as the second serial
data output when the SCO_EN input is a logic-low level. This
output functions as the serial clock output when the SCO_EN
input is a logic-high level. The SCO_EN input has an internal
pull-down device and the default state of SCO_EN is low (se-
rial data output 2 enabled). SCO/SDO2 is muted when the
MUTE input is a logic low level. When the Bypass mode is
activated and this output is functioning as a serial clock out-
put, the output will also be muted.
Control Inputs and Indicator
Outputs
SERIAL DATA RATE SELECTOR
The Serial Data Rate Selector (RATE [1:0]) permits the user
to fix the operating serial data rate. The pins have internal pull-
downs which maintain a logic-low input condition unless ex-
ternally driven to a logic-high condition. This input also serves
to place the device in a test mode. The codes shown in Table
1 select the desired operating serial data rate. The LMH0356
then enters either the Auto-Rate Detect mode or a single op-
erating rate. Selecting the 270 Mbps rate mode may also be
used when reclocking DVB-ASI data. DVB-ASI data is
MPEG2 coded data that is transmitted in 8B10B coding. The
device will reclock this data without harmonic locking.
TABLE 1. Data Rate Select Input Codes
RATE [1:0] Data Rate
Code
or Mode
Comments
00 Auto-Rate
Detect
mode
01 270 Mbps May be used to support DVB-
ASI operation
10 1483/1485
Mbps,
2967/2970
Mbps
11 www.national.com

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