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PDF ADJD-S371-QR999 Data sheet ( Hoja de datos )
| Número de pieza | ADJD-S371-QR999 | |
| Descripción | Miniature Surface-Mount RGB Digital Color Sensor Module | |
| Fabricantes | AVAGO TECHNOLOGIES LIMITED | |
| Logotipo |  |
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ADJD-S371-QR999
Miniature Surface-Mount
RGB Digital Color Sensor Module
Data Sheet
Description
ADJD-S371-QR999 is a cost effective, 4 channel digital
output RGB+CLEAR sensor in miniature surface-mount
package with a mere size of 3.9 x 4.5 x 1.8 mm. It is
an IC module with combination of White LED and
CMOS IC with integrated RGB filters + Clear channel and
analog-to-digital converter front end.
It is ideal for applications like color detection, mea-
surement, illumination sensing for display backlight
adjustment such as colors, contrast and brightness
enhancement in mobile devices which demand higher
package integration, small footprint and low power
consumption.
The 2-wire serial output allows direct interface to
microcontroller or other logic control for further signal
processing without additional component such as
analog to digital converter. With the wide sensing
range of 100 lux to 100,000 lux, the sensor can be used
for many applications with different light levels by
adjusting the gain setting. Additional features include
a selectable sleep mode to minimize current con-
sumption when the sensor is not in use.
Features
• Four channel integrated light to digital converter
(Red, Green, Blue and Clear).
• 10 bit digital output resolution
• Independent gain selection for each channel
• Wide sensitivity coverage: 0.1 klux - 100 klux
• Two wire serial communication
• Built in oscillator/selectable external clock
• Low power mode (sleep mode)
• Small 3.9 x 4.5 x 1.8 mm module
• Integrated solution with sensor, LED and separator
in module for ease of design
• Lead free
Applications
• Mobile appliances
• Consumer appliances
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Saturation Irradiance for Maximum Sensitivity [12]
Parameter Symbol Conditions
Minimum
Saturation
Irradiance
lP = 460 nm
Refer Note 9
lP = 542 nm
Refer Note 10
lP = 645 nm
Refer Note 11
B
G
R
lP = 645 nm Clear
Refer Note 11
Typical (Note 3)
0.27
0.22
0.16
0.16
Maximum
Units
mW/cm2
Notes:
1. The “Absolute Maximum Ratings” are those values beyond which damage to the device may occur. The device should not be operated at
these limits. The parametric values defined in the “Electrical Specifications” table are not guaranteed at the absolute maximum ratings. The
“Recommended Operating Conditions” table will define the conditions for actual device operation.
2. Unless otherwise specified, all voltages are referenced to ground.
3. Specified at room temperature (25°C) and VDDD = VDDA = 2.5 V.
4. Applies to all DI pins.
5. Applies to all DO pins. SDASLV go tri-state when output logic high. Minimum VOH depends on the pull-up resistor value.
6. Applies to all DO and DIO pins.
7. Refers to total device current consumption.
8. Output and bidirectional pins are not loaded.
9. Test condition is blue light of peak wavelength (lP) 460 nm and spectral half width (l1/2) 25 nm.
10. Test condition is green light of peak wavelength (lP) 542 nm and spectral half width (l1/2) 35 nm.
11. Test condition is red light of peak wavelength (lP) 645 nm and spectral half width (l1/2) 20 nm.
12. Saturation irradiance = (MSB)/(Irradiance responsivity).
1.0
0.8
0.6
0.4
0.2
0
400 420 440 460 480 500 520 540 560 580 600 620 640 660 680 700
WAVELENGTH (nm)
Figure 1. Typical spectral response when the gains for all the color channels are set at equal
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To read from a register, the master first generates a START
condition. Then it sends the slave address for the device
it wants to communicate with. The least significant bit
(LSB) of the slave address must indicate that the master
wants to write to the slave. The addressed device will
then acknowledge the master.
The master writes the register address it wants to access
and waits for the slave to acknowledge. The master then
generates a repeated START condition and resends the
slave address sent previously. The least significant bit
(LSB) of the slave address must indicate that the master
wants to read from the slave. The addressed device will
then acknowledge the master.
The master reads the register data sent by the slave and
sends a no acknowledge signal to stop reading. The
master then generates a STOP condition to end the data
transfer.
START
CONDITION
MASTER WILL WRITE DATA
REPEATED START
CONDITION
MASTER WILL READ DATA
STOP
CONDITION
S A6 A5 A4 A3 A2 A1 A0 W A D7 D6 D5 D4 D3 D2 D1 D0 A Sr A6 A5 A4 A3 A2 A1 A0 R A D7 D6 D5 D4 D3 D2 D1 D0 A P
MASTER SENDS
SLAVE ADDRESS
MASTER WRITES
REGISTER ADDRESS
MASTER SENDS
SLAVE ADDRESS
MASTER READS
REGISTER DATA
SLAVE ACKNOWLEDGE
SLAVE ACKNOWLEDGE
SLAVE ACKNOWLEDGE
MASTER NOT
ACKNOWLEDGE
Figure 11. Register byte read protocol
11
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| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet ADJD-S371-QR999.PDF ] | |
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