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PDF MD5811-D256-V3Q18 Data sheet ( Hoja de datos )
| Número de pieza | MD5811-D256-V3Q18 | |
| Descripción | Mobile Diskonchip P3 | |
| Fabricantes | M-Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MD5811-D256-V3Q18 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Mobile DiskOnChip P3
256Mb Flash Disk with
M-Systems’ x2 Technology
Preliminary Data Sheet, June 2003
Highlights
Mobile DiskOnChip™ P3, a member of
M-Systems’ DiskOnChip™ family of
optimized memory solutions for new-generation
mobile handsets, provides high performance
and reliability using NAND flash technology. It
combines Toshiba’s cutting-edge 0.13 micron
NAND flash manufacturing process enhanced
for performance and reliability with
M-Systems’ x2 technology.
Mobile DiskOnChip P3 optimizes real estate
and cost structure by incorporating the flash
array and an embedded thin controller in a
single die. A boot block can be used to boot the
OS or initialize the CPU/platform, replacing
expensive NOR flash and further reducing
memory system costs.
Mobile DiskOnChip P3 provides:
Flash disk for both code and data storage
Low voltage: 1.8V or 3.3 I/O (auto-detect),
3V Core
Hardware protection and security-enabling
features
High capacity: 256Mbit (32MByte)
Device cascading option: up to 1Gbit
(128MByte)
Enhanced Programmable Boot Block
enabling eXecute In Place (XIP)
functionality using 16-bit interface
Small form factors:
48-pin TSOP-I package
85-ball FBGA 7x10x1.2 mm package
Enhanced performance with:
Multi-plane operation
DMA support
MultiBurst operation
Turbo operation
Unrivaled data integrity with a robust Error
Detection Code/Error Correction Code
(EDC/ECC)
Maximized flash endurance with TrueFFS®
6.1 (and higher) flash management software
Support for major mobile OSs, including:
Symbian OS, Pocket PC 2002/3,
Smartphone 2002/3, Palm OS, Nucleus,
Linux, Windows CE
Compatible with major mobile CPUs,
including TI OMAP, XScale, Motorola
DragonBall MX1 and Qualcomm
MSMxxxx.
1
Preliminary Data Sheet, Rev. 0.3
93-SR-009-8L
1 page  
www.datasheet4u.com
Mobile DiskOnChip P3
4.4 Turbo Operation ............................................................................................................... 31
5. Hardware Protection ............................................................................................................... 32
5.1 Method of Operation......................................................................................................... 32
5.2 Low-Level Structure of the Protected Area....................................................................... 33
6. Modes of Operation................................................................................................................. 35
6.1 Normal Mode .................................................................................................................... 36
6.2 Reset Mode ...................................................................................................................... 36
6.3 Deep Power-Down Mode ................................................................................................. 36
7. TrueFFS Technology............................................................................................................... 38
7.1 General Description.......................................................................................................... 38
7.1.1 Built-In Operating System Support..................................................................................... 39
7.1.2 TrueFFS Software Development Kit (SDK)........................................................................ 39
7.1.3 File Management................................................................................................................ 39
7.1.4 Bad Block Management ..................................................................................................... 39
7.1.5 Wear-Leveling .................................................................................................................... 39
7.1.6 Power Failure Management ............................................................................................... 40
7.1.7 Error Detection/Correction.................................................................................................. 40
7.1.8 Special Features Through I/O Control (IOCTL) Mechanism.............................................. 41
7.1.9 Compatibility ....................................................................................................................... 41
7.2 8KB Memory Window ....................................................................................................... 41
8. Register Descriptions ............................................................................................................. 42
8.1 Definition of Terms ........................................................................................................... 42
8.2 Reset Values .................................................................................................................... 42
8.3 No Operation (NOP) Register........................................................................................... 43
8.4 Chip Identification (ID) Register [0:1]................................................................................ 43
8.5 Test Register .................................................................................................................... 43
8.6 Bus Lock Register ............................................................................................................ 44
8.7 Endian Control Register ................................................................................................... 45
8.8 DiskOnChip Control Register/Control Confirmation Register ........................................... 46
8.9 Device ID Select Register................................................................................................. 47
8.10 Configuration Register...................................................................................................... 47
8.11 Interrupt Control Register ................................................................................................. 48
8.12 Interrupt Status Register................................................................................................... 49
8.13 Output Control Register.................................................................................................... 50
8.14 DPD Control Register ....................................................................................................... 51
2
Data Sheet, Rev. 0.3
93-SR-009-8L
5 Page 
www.datasheet4u.com
Mobile DiskOnChip P3
7x10 FBGA Package
12345678
A MM
MM
B M M MM MMM M
CA
A7
RSRVD
RSRVD
WE#
A8
A11
D A3
A6
RSRVD
RSTIN#
RSRVD
RSRVD
A12
RSRVD
E A2
A5
RSRVD
BUSY#
RSRVD
A9
LOCK#
RSRVD
F A1 A4 IF_CFG M
M A10 ID0 IRQ#
G A0/
DPD
VSS
D1
M
M D6 DMARQ# ID1
H CE# OE# D9 D3
D4 D13 D15 RSRVD
J RSRVD
D0
D10
VCC
VCCQ
D12
D7
VSS
K D8 D2 D11 CLK D5 D14
L M M MM MMM M
M MM
MM
Figure 2: 7x10 FBGA Ballout for Standard Interface (Mobile DiskOnChip P3 256Mb)
8
Data Sheet, Rev. 0.3
93-SR-009-8L
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MD5811-D256-V3Q18.PDF ] | |
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