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PDF PLL520-20 Data sheet ( Hoja de datos )
| Número de pieza | PLL520-20 | |
| Descripción | Low Phase Noise VCXO | |
| Fabricantes | PhaseLink Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PLL520-20 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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Preliminary PLL520-20
Low Phwww.DataSheet4U.com ase Noise VCXO (for 100-200MHz Fundamental Crystals)
FEATURES
• 100MHz to 200MHz Fundamental Mode Crystal.
• Output range: 100MHz – 200MHz (no PLL).
• Low Injection Power for crystal 50uW.
• Complementary outputs: CMOS, PECL or LVDS.
• Selectable OE Logic (enable high or enable low).
• Integrated variable capacitors.
• Supports 2.5V or 3.3V-Power Supply.
• Available in die form.
• Die thickness is 10 mil.
DESCRIPTIONS
PLL520-20 is a VCXO IC specifically designed to
pull high frequency fundamental crystals. Its design
was optimized to tolerate higher limits of
interelectrodes capacitance and bonding
capacitance to improve yield. It achieves very low
current into the crystal resulting in better overall
stability. Its internal varicaps allow an on chip
frequency pulling, controlled by the VCON input.
BLOCK DIAGRAM
VCON Oscillator
Amplifier
X+
w/
integrated
varicaps
X-
OE
Q
Q
PLL520-20
DIE CONFIGURATION
65 mil
25 24 23 22 21 20 19 18
XIN 26
XOUT 27
Die ID:
A1919-19B
DNC 28
DNC 29
OE
CTRL 30
VCON 31
C502A
12345 6 78
(1550,1475)
17 GNDBUF
16 N/C
15 LVDSB
14 PECLB
13 VDDBUF
12 VDDBUF
11 PECL
10 LVDS
9 OUTSEL^
Y (0,0)
X
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
OUTPUT SELECTION AND ENABLE
Pad #18
OUTSEL1
0
0
1
1
Pad #25
OUTSEL0
0
1
0
1
Selected Output
High Drive CMOS
Standard CMOS
LVDS
PECL (default)
OE_SELECT
(Pad #9)
OE_CTRL
(Pad #30)
State
0
0 Tri-state
1 (Default) Output enabled
1 (Default)
0 (Default) Output enabled
1 Tri-state
Pad #9, 18, 25: Bond to GND to set to “0”, bond to VDD to set to “1”
No connection results to “default” setting through internal pull-up/-down.
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is “1”
Logical states defined by CMOS levels if OE_SELECT is “0”
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 1
1 page  
Preliminary PLL520-20
Low Phwww.DataSheet4U.com ase Noise VCXO (for 100-200MHz Fundamental Crystals)
9. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
VOH
VOL
CONDITIONS
RL = 50 Ω to (VDD – 2V)
(see figure)
10. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
tr
tf
CONDITIONS
@20/80% - PECL
@80/20% - PECL
MIN.
VDD – 1.025
MAX.
VDD – 1.620
MIN. TYP. MAX.
0.6 1.5
0.5 1.5
UNITS
V
V
UNITS
ns
ns
PECL Levels Test Circuit
OUT
50Ω
VDD
2.0V
PECL Output Skew
OUT
50%
OUT
50Ω
OUT
80%
50%
20%
OUT
tR
OUT
tSKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PLL520-20.PDF ] | |
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