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PDF SH7660 Data sheet ( Hoja de datos )
| Número de pieza | SH7660 | |
| Descripción | 32-Bit RISC Microcomputer | |
| Fabricantes | Renesas Technology | |
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SH7660
Hardware Manual
Renesas 32-Bit RISC Microcomputer
HD6417660
Rev.1.00
2004.2.6
1 page  
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
www.DataSheet4iiU).cIonmput/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each
section includes notes in relation to the descriptions given, and usage notes are given, as required,
as the final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
Rev. 1.00, 02/04, page v of xxxviii
5 Page 
4.4 Exception Processing While DSP Extension Function is Valid........................................ 168
4.4.1 Illegal Instruction Exception and Slot Illegal Instruction Exception ................... 168
4.4.2 CPU Address Error .............................................................................................. 168
4.4.3 Exception in Repeat Control Period..................................................................... 168
4.5 Usage Notes ...................................................................................................................... 175
Section 5 Cache .................................................................................................177
5.1 Features............................................................................................................................. 177
5.1.1 Cache Structure.................................................................................................... 177
5.2 Register Descriptions ........................................................................................................ 179
5.2.1 Cache Control Register 1 (CCR1) ....................................................................... 179
5.2.2 Cache Control Register 2 (CCR2) ....................................................................... 180
5.3 Operation .......................................................................................................................... 183
5.3.1 Searching the Cache............................................................................................. 183
5.3.2 Read Access......................................................................................................... 184
5.3.3 Prefetch Operation ............................................................................................... 184
5.3.4 Write Access ........................................................................................................ 184
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5.3.5 Write-Back Buffer ............................................................................................... 185
5.3.6 Coherency of Cache and External Memory ......................................................... 185
5.4 Memory-Mapped Cache ................................................................................................... 186
5.4.1 Address Array ...................................................................................................... 186
5.4.2 Data Array ........................................................................................................... 187
5.4.3 Usage Examples................................................................................................... 189
Section 6 X/Y Memory......................................................................................191
6.1 Features............................................................................................................................. 191
6.2 Operation .......................................................................................................................... 192
6.2.1 Access from CPU................................................................................................. 192
6.2.2 Access from DSP ................................................................................................. 192
6.2.3 Access from I Bus Master Module ...................................................................... 193
6.3 Usage Notes ...................................................................................................................... 193
6.3.1 Page Conflict ....................................................................................................... 193
6.3.2 Bus Conflict ......................................................................................................... 193
6.3.3 Cache Settings...................................................................................................... 193
6.3.4 Sleep Mode .......................................................................................................... 194
Section 7 U Memory..........................................................................................195
7.1 Features............................................................................................................................. 195
7.2 Operation .......................................................................................................................... 196
7.2.1 Access from CPU................................................................................................. 196
7.2.2 Access from DSP ................................................................................................. 196
7.2.3 Access from I Bus Master Module ...................................................................... 196
7.3 Usage Notes ...................................................................................................................... 197
Rev. 1.00, 02/04, page xi of xxxviii
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