|
|
PDF ADC08B200 Data sheet ( Hoja de datos )
| Número de pieza | ADC08B200 | |
| Descripción | 200 MSPS A/D Converter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ADC08B200 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
June 2008
ADC08B200
8-Bit, 200 MSPS A/D Converter with Capture Buffer
General Description
The ADC08B200 is a high speed analog-to-digital converter
(ADC) with an integrated capture buffer. The 8-bit, 200 MSPS
A/D core is based upon the proven ADC08200 with integrated
track-and-hold and is optimized for low power consumption.
This device contains a selectable size capture buffer of up to
1,024 bytes that allows fast capture of an input signal with a
slower readout rate. An on-chip clock PLL circuit provides the
www.DataSheeot4pUtio.cnomof on-chip clock rate multiplication to provide the high
speed sampling clock.
The ADC08B200 is resistant to latch-up and the outputs are
short-circuit proof. The top and bottom of the ADC08B200's
reference ladder are available for connections, enabling a
wide range of input possibilities. The digital outputs are TTL/
CMOS compatible with a separate output power supply pin to
support interfacing with 2.7V to 3.3V logic. The digital inputs
and outputs are low voltage TTL/CMOS compatible and the
output data format is straight binary.
The ADC08B200 is offered in a 48-pin plastic package
(TQFP) and is specified over the extended industrial temper-
ature range of −40°C to +105°C. An evaluation board is
available to assist in the easy evaluation of the ADC08B200.
Features
■ Single-ended input
■ Selectable capture buffer size
■ PLL for clock multiplication
■ Reference Ladder Top and Bottom accessible
■ Linear power scaling with sample rate
■ FPGA training pattern
■ Power-down feature
Key Specifications
(PLL Bypassed)
■ Resolution
■ Maximum sampling frequency
■ DNL
■ ENOB (fIN= 49 MHz)
■ THD (fIN= 49 MHz)
■ Power Consumption
— Operating, 50 MHz Input
— Power Down
8 Bits
200 MSPS (min)
±0.4 LSB (typ)
7.2 bits (typ)
−53 dBc (typ)
2 mW / Msps (typ)
2.15 mW (typ)
Applications
■ Laser Ranging
■ RADAR
■ Pulse Capturings
Pin Configuration
© 2007 National Semiconductor Corporation 202147
20214701
www.national.com
1 page  
Absolute Maximum Ratings
(Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VA, VP, VD, VDR)
Driver Supply Voltage (VDR)
Voltage on Any Input or Output Pin
Reference Voltage (VRT, VRB)
Input Current, Data Outputs
Input Current all other pins (Note 3)
Package Input Current (Note 3)
Power Dissipation at TA = 25°C
ESD Susceptibility (Note 5)
www.DataSheHeut4mUa.ncoBmody Model
Machine Model
Charged Device Model
Soldering Temperature, Infrared,
10 seconds (Note 6)
Storage Temperature
-0.3V to 3.8V
-0.3V to VA +0.3V
−0.3V to VA
GND to VA
±1 mA
±25 mA
±50 mA
See (Note 4)
2500V
200V
1000V
235°C
−65°C to +150°C
Operating Ratings (Notes 1, 2)
Operating Temperature Range
Supply Voltage (VA)
Driver Supply Voltage (VDR)
Maximum Supply Voltage
VD, VP
CLK Frequency
PLL Bypassed
PLL used
−40°C ≤ TA ≤ +105°C
+3.0V to +3.6V
+2.7V to (VA + 0.3V)
VA + 0.3V
1 to 210 MHz
15 to 105 MHz
RCLK Frequency (Note 12)
2 - 210 MHz
RCLK Duty Cycle
35% to 65%
Ground Difference |GND - DR GND|
0V to 300 mV
Upper Reference Voltage (VRT)
Lower Reference Voltage (VRB)
Reference Delta (VRT − VRB)
VIN Voltage Range
0.5V to (VA − 0.3V)
0V to (VRT − 0.5V)
0.5V to 2.3V
VRB to VRT
Package Thermal Resistance
Package
48-Lead TQFP
θJA
76 °C/W
Converter Electrical Characteristics
The following specifications apply for VA = VD = VP = VDR = +3.3VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 200 MHz at 50%
duty cycle, OEDGE/TEN = 1, Buffer and PLL bypassed. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C
(Notes 7, 8)
Symbol
Parameter
Conditions
Typical Limits
(Note 9) (Note 9)
Units
(Limits)
DC ACCURACY
INL Integral Non-Linearity
±0.55 ±1.3 LSB (max)
DNL
Differential Non-Linearity
±0.40 ±0.9 LSB (max)
Missing Codes
0 (max)
FSE Full Scale Error
−39
−80 mV (min)
0 mV (max)
VOFF
Zero Scale Offset Error
ANALOG INPUT AND REFERENCE CHARACTERISTICS
55 70 mV (max)
VIN Input Voltage
CIN VIN Input Capacitance
(CLK LOW)
VIN = 0.75V +0.5 Vrms (CLK HIGH)
1.6 VRB V (min)
VRT V (max)
3 pF
4 pF
RIN
FPBW
Analog Input Resistance
Full Power Bandwidth
>1 MΩ
500 MHz
VRT Top Reference Voltage
1.9 VA V (max)
0.5 V (min)
VRB Bottom Reference Voltage
0.3 VRT − 0.5 V (max)
0 V (min)
VRT - VRB Reference Voltage Delta
0.5 V (min)
1.6
2.3 V (max)
RREF
Reference Ladder Resistance
VRT to VRB
145 Ω (min)
160
200 Ω (max)
5 www.national.com
5 Page 
Timing Diagrams (PLL Bypassed)
www.DataSheet4U.com
ADC08B200 Data Capture and Read Operation
20214757
ADC08B200 Capture and Write Enable Timing
20214731
ADC08B200 Buffer Write Timing
20214754
11 www.national.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADC08B200.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ADC08B200 | 200 MSPS A/D Converter | National Semiconductor |
| ADC08B200 | 8-Bit 200 MSPS A/D Converter with Capture Buffer (Rev. F) |  Texas Instruments |
| ADC08B200-Q1 | ADC08B200 / ADC08B200Q 8-Bit 200 MSPS A/D Converter with Capture Buffer (Rev. F) | Texas Instruments |
| ADC08B200Q | 8-Bit 200 MSPS A/D Converter with Capture Buffer (Rev. F) | Texas Instruments |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |