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PDF MCF51QE64 Data sheet ( Hoja de datos )
| Número de pieza | MCF51QE64 | |
| Descripción | 32-Bit Version 1 ColdFire Central Processor | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF51QE128
Rev. 7, 10/2008
MCF51QE128 Series
Covers: MCF51QE128, MCF51QE96, MCF51QE64,
MCF51QE32
• 32-Bit Version 1 ColdFire® Central Processor Unit (CPU)
– Up to 50.33-MHz ColdFire V1 CPU above 2.4V,
40-MHz CPU above 2.1V, and 20-MHz CPU above
1.8V, across temperature range
– Provides 0.94 Dhrystone 2.1 MIPS per MHz
www.DataSheet4U.copmerformance when running from internal RAM
(0.76 DMIPS/MHz from flash)
– Implements Instruction Set Revision C (ISA_C)
– Support for up to 30 peripheral interrupt requests and
seven software interrupts
• On-Chip Memory
– Flash read/program/erase over full operating voltage
and temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to
RAM and flash contents
• Power-Saving Modes
– Two low power stop modes; reduced power wait mode
– Peripheral clock enable register can disable clocks to
unused modules, reducing currents; allows clocks to
remain enabled to specific peripherals in stop3 mode
– Very low power external oscillator can be used in stop3
mode to provide accurate clock to active peripherals
– Very low power real time counter for use in run, wait,
and stop modes with internal and external clock sources
– 6 μs typical wake up time from stop modes
• Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator;
Crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 16 MHz
– Internal Clock Source (ICS) — FLL controlled by
internal or external reference; precision trimming of
internal reference allows 0.2% resolution and 2%
deviation; supports CPU freq. from 2 to 50.33 MHz
• System Protection
– Watchdog computer operating properly (COP) reset
with option to run from dedicated 1-kHz internal clock
source or bus clock
– Low-voltage detection with reset or interrupt; selectable
trip points
– Illegal opcode and illegal address detection with
programmable reset or exception response
– Flash block protection
MCF51QE128
80-LQFP
Case 917A
14 mm2
64-LQFP
Case 840F
10 mm2
• Development Support
– Single-wire background debug interface
– 4 PC plus 2 address (optional data) breakpoint registers
with programmable 1- or 2-level trigger response
– 64-entry processor status and debug data trace buffer
with programmable start/stop conditions
• ADC — 24-channel, 12-bit resolution; 2.5 μs conversion
time; automatic compare function; 1.7 mV/°C temperature
sensor; internal bandgap reference channel; operation in
stop3; fully functional from 3.6V to 1.8V
• ACMPx — Two analog comparators with selectable
interrupt on rising, falling, or either edge of comparator
output; compare option to fixed internal bandgap reference
voltage; outputs can be optionally routed to TPM module;
operation in stop3
• SCIx — Two SCIs with full duplex non-return to zero
(NRZ); LIN master extended break generation; LIN slave
extended break detection; wake up on active edge
• SPIx— Two serial peripheral interfaces with Full-duplex or
single-wire bidirectional; Double-buffered transmit and
receive; MSB-first or LSB-first shifting
• IICx — Two IICs with; Up to 100 kbps with maximum bus
loading; Multi-master operation; Programmable slave
address; Interrupt driven byte-by-byte data transfer;
supports broadcast mode and 10 bit addressing
• TPMx — One 6-channel and two 3-channel; Selectable
input capture, output compare, or buffered edge- or
center-aligned PWMs on each channel
• RTC — 8-bit modulus counter with binary or decimal
based prescaler; External clock source for precise time
base, time-of-day, calendar or task scheduling functions;
Free running on-chip low power oscillator (1 kHz) for
cyclic wake-up without external components
• Input/Output
– 70 GPIOs and 1 input-only and 1 output-only pin
– 16 KBI interrupts with selectable polarity
– Hysteresis and configurable pull-up device on all input
pins; Configurable slew rate and drive strength on all
output pins.
– SET/CLR registers on 16 pins (PTC and PTE)
– 16 bits of Rapid GPIO connected to the CPU’s
high-speed local bus with set, clear, and toggle
functionality
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
1 page  
Pin Assignments
2 Pin Assignments
This section describes the pin assignments for the available packages. See Table 1 for pin availability by package pin-count.
www.DataSheet4U.com
PTD1/KBI2P1/MOSI2
PTD0/KBI2P0/SPSCK2
PTH7/SDA2
PTH6/SCL2
PTH5
PTH4
PTE7/RGPIO7/TPM3CLK
VDD
VDDAD
VREFH
VREFL
VSSAD
VSS
PTB7/SCL1/EXTAL
PTB6/SDA1/XTAL
PTH3
PTH2
PTH1
PTH0
PTE6/RGPIO6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60 PTA2/KBI1P2/SDA1/ADP2
59 PTA3/KBI1P3/SCL1/ADP3
58 PTD2/KBI2P2/MISO2
57 PTD3/KBI2P3/SS2
56 PTD4/KBI2P4
55 PTJ0
54 PTJ1
53 PTF0/ADP10
52 PTF1/ADP11
51 VSS
50 VDD
49 PTE4/RGPIO4
48 PTA6/TPM1CH2/ADP8
47 PTA7/TPM2CH2/ADP9
46 PTF2/ADP12
45 PTF3/ADP13
44 PTJ2
43 PTJ3
42 PTB0/KBI1P4/RxD1/ADP4
41 PTB1/KBI1P5/TxD1/ADP5
Pins in bold are added from the next smaller package.
Figure 2. Pin Assignments in 80-Pin LQFP
Freescale Semiconductor
MCF51QE128 Series Data Sheet, Rev. 7
5
5 Page 
Electrical Characteristics
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Eqn. 1
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected)
is:
www.DataSheet4U.com
PD = K ÷ (TJ + 273°C)
Solving Equation 1 and Equation 2 for K gives:
Eqn. 2
K = PD × (TA + 273°C) + θJA × (PD)2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively
for any value of TA.
3.5 ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 6. ESD and Latch-up Test Conditions
Model
Description
Human
Body
Series resistance
Storage capacitance
Number of pulses per pin
Series resistance
Machine Storage capacitance
Number of pulses per pin
Minimum input voltage limit
Latch-up
Maximum input voltage limit
Symbol
R1
C
—
R1
C
—
Value
1500
100
3
0
200
3
– 2.5
7.5
Unit
Ω
pF
Ω
pF
V
V
Freescale Semiconductor
MCF51QE128 Series Data Sheet, Rev. 7
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MCF51QE64.PDF ] | |
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