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PDF FPD750SOT343 Data sheet ( Hoja de datos )
| Número de pieza | FPD750SOT343 | |
| Descripción | LOW NOISE HIGH LINEARITY PACKAGED PHEMT | |
| Fabricantes | Filtronic Compound Semiconductors | |
| Logotipo |  |
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FPD750SOT343
LOW NOISE HIGH LINEARITY PACKAGED PHEMT
PACKAGE:
FEATURES (1850MHZ):
• 0.5 dB N.F.min.
• 20 dBm Output Power (P1dB)
• 16.5 dB Small-Signal Gain (SSG)
• 37 dBm Output IP3
• RoHS compliant (Directive 2002/95/EC)
Datasheet v3.0
ROHS:
9
GENERAL DESCRIPTION:
www.DataSheet4U.cTohme FPD750SOT343 is a packaged depletion
mode pseudomorphic High Electron Mobility
Transistor (pHEMT). It utilizes a 0.25 µm x 750
µm Schottky barrier Gate. The Filtronic
0.25µm process ensures class-leading noise
performance. The use of a small footprint
plastic package allows for cost effective
system implementation.
TYPICAL APPLICATIONS:
• 802.11a,b,g and WiMax LNAs
• PCS/Cellular High Linearity LNAs
• Other types of wireless infrastructure systems.
TYPICAL PERFORMANCE1:
RF PARAMETER
SYMBOL
Power at 1dB Gain Compression
OP1dB
Small Signal Gain
SSG
CONDITIONS
VDS = 3.3 V; IDS = 40mA
VDS = 3.3 V; IDS = 40mA
0.9GHZ 1.85GHZ 2.6GHZ 3.5GHZ UNITS
20 19 20 20.5 dBm
22 16.5 14
11 dB
Power-Added Efficiency
Maximum Stable Gain (|S21/S12|)
Noise Figure
Output Third-Order Intercept Point
POUT = 9 dBm per Tone
PAE
MSG
N.F.
OIP3
VDS = 3.3 V; IDS = 40mA
POUT = P1dB
VDS = 3.3 V; IDS = 40mA
VDS = 3.3 V; IDS = 40mA
VDS = 3.3V; IDS = 40mA
VDS = 3.3V; IDS = 80mA
50
24
0.5
32
35
45 45
20 18
0.6 0.7
31 31
37 35
50 %
16 dB
0.8 dB
32
dBm
38
ELECTRICAL SPECIFICATIONS2:
RF/DC PARAMETER
SYMBOL
Frequency
f
Power at 1dB Gain Compression
P1dB
Small Signal Gain
SSG
Saturated Drain-Source Current
IDSS
Transconductance
GM
Pinch-Off Voltage
|VP|
Gate-Source Breakdown Voltage
|VBDGS|
Gate-Drain Breakdown Voltage
|VBDGD|
Thermal Resistivity (see Notes)
θJC
CONDITIONS
VDS = 3.3 V; IDS = 40mA
VDS = 3.3 V; IDS = 40mA
VDS = 1.3 V; VGS = 0 V
VDS = 1.3 V; VGS = 0 V
VDS = 1.3 V; IDS = 0.75 mA
IGS = 0.75 mA
IGD = 0.75 mA
VDS > 3V
MIN
17
16
185
0.7
13
13
TYP
2.0
230
200
1.0
16
18
143
MAX
280
1.3
UNITS
GHz
dBm
dB
mA
mS
V
V
V
°C/W
Note: 1. Based on measured data taken on applications circuits. 2. All devices are 100% RF and DC tested at
2GHz with ZS = ZL = 50 Ohms 3. TAMBIENT = 22°C
1
Tel: +44 (0) 1325 301111
Specifications subject to change without notice
Filtronic Compound Semiconductors Ltd
Fax: +44 (0) 1325 306177
Email: [email protected]
Website: www.filtronic.com
1 page  
REFERENCE DESIGN (0.9GHZ):
FPD750SOT343
Datasheet v3.0
FREQUENCY
Gain
P1dB
OIP31
N.F.
S11
www.DataSheet4U.com S22
Vd
Vg
Id
GHZ
dB
dBm
dBm
dB
dB
dB
V
V
mA
0.9
22
20
32
0.5
-5
-10
3.3
-0.4 to -0.6
40
1. OIP3 measured at Pout of 9dBm per
tone
BOARD LAYOUT:
Measured Gain and Return Loss
Vg Vd
0.01uF
15pF
20O
+ 1.0uF
15pF 0.01uF +
Lg Ld
33pF L1
L2 33pF
Q1
0.63"
1.45"
Component Values
Component
Lg
Ld
L1
L2
Value
56nH
56nH
15nH
4.7nH
Description
LL1608 Toko chip inductor
LL1608 Toko chip inductor
LL1608 Toko chip inductor
LL1608 Toko chip inductor
Eval board material - 31mil thick FR4 with 1/2 Ounce Cu on
both sides
FPD750SOT343 EVAL Board -Vg
Schematic
@ 900MHz
0.01uF
15pF
20 Ohm
Vd
1.0uF
0.01uF
15pF
33pF
RF IN
56 nH 56 nH
L1 L2
33pF
RF OUT
D.C. Blocking capacitors are ATC series 600S. A tantalum 1.0µF is used at the drain terminal. All
other capacitors are 0603 and 0805 standard chip capacitors. A 0603 size 20 Ohm Chip resistor from
Vishay is used on the gate D.C. bias line for stability.
5
Tel: +44 (0) 1325 301111
Specifications subject to change without notice
Filtronic Compound Semiconductors Ltd
Fax: +44 (0) 1325 306177
Email: [email protected]
Website: www.filtronic.com
5 Page 
PCB FOOT PRINT
FPD750SOT343
Datasheet v3.0
profile defined within IPC/JEDEC J-STD-020C,
Moisture / Reflow sensitivity classification for
non-hermetic solid state surface mount devices
APPLICATION NOTES & DESIGN DATA:
www.DataSheet4U.com
Application Notes and design data including S-
parameters, noise parameters and device
model are available on request.
RELIABILITY:
Units in inches
A MTTF of 4.2 million hours at a channel
temperature of 150°C is achieved for the
process used to manufacture this device.
DISCLAIMERS:
PREFERRED ASSEMBLY INSTRUCTIONS:
This package is compatible with both lead free
and leaded solder reflow processes as defined
within IPC/JEDEC J-STD-020C. The maximum
package temperature should not exceed
260°C.
HANDLING PRECAUTIONS:
To avoid damage to the devices care should
be exercised during handling. Proper
Electrostatic Discharge (ESD) precautions
should be observed at all stages of storage,
handling, assembly, and testing.
ESD/MSL RATING:
This product is not designed for use in any
space based or life sustaining/supporting
equipment.
ORDERING INFORMATION:
PART NUMBER
FPD750SOT343
FPD750SOT343E
FPD750SOT343CE
EB750SOT343-BB
EB750SOT343-BA
EB750SOT343-BC
EB750SOT343-BE
EB750SOT343-BG
EB750SOT343-AH
DESCRIPTION
Packaged pHEMT
Lead free Packaged pHEMT
RoHS Compliant Packaged pHEMT
with enhanced passivation
(Recommended for New Designs)
0.9 GHz evaluation board
1.85 GHz evaluation board
2.0 GHz evaluation board
2.4 GHz evaluation board
2.6 GHz evaluation board
3.5 GHz evaluation board
These devices should be treated as Class 1A
(250V - 500V) using the human body model as
defined in JEDEC Standard No. 22-A114.
The device has a MSL rating of Level 1. To
determine this rating, preconditioning was
performed to the device per, the Pb-free solder
11
Tel: +44 (0) 1325 301111
Specifications subject to change without notice
Filtronic Compound Semiconductors Ltd
Fax: +44 (0) 1325 306177
Email: [email protected]
Website: www.filtronic.com
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet FPD750SOT343.PDF ] | |
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