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PDF CY7C9915 Data sheet ( Hoja de datos )
| Número de pieza | CY7C9915 | |
| Descripción | 3.3V Programmable Skew Clock Buffer | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
CY7C9915
3.3V Programmable Skew Clock Buffer
Features
• All output pair skew <100 ps (typical)
• Input Frequency Range: 3.75 MHz to 150 MHz
• Output Frequency Range: 3.75 MHz to 150 MHz
• User-selectable output functions
— Selectable skew to 18 ns
— Inverted and non-inverted
— Operation at 1⁄2 and 1⁄4 input frequency
— Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
www.DataS•heZerto4Uin.pcuotm-to-output delay
• 3.3V power supply
• ± 3.0% Output Duty Cycle Distortion
• LVTTL outputs drive 50Ω terminated lines
• Low operating current
• 32-pin PLCC package
• Jitter < 100ps peak-to-peak (< 15 ps RMS)
Block Diagram
TEST
FB
REF
PHASE
FREQ FILTER
DET
FS
VCO AND
TIME UNIT
GENERATOR
4F0
4F1 SELECT
INPUTS
(THREE
3F0 LEVEL)
3F1
2F0
2F1
SKEW
SELECT
MATRIX
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
Functional Description
The CY7C9915 RoboClock is a 150-MHz Low-voltage
Programmable Skew Clock Buffer that offers user-selectable
control over system clock functions. This multiple-output clock
driver provides the system integrator with functions necessary
to optimize the timing of high-performance computer systems.
Eight individual drivers, arranged as four pairs of user-control-
lable outputs, can each drive terminated transmission lines
with impedances as low as 50Ω while delivering minimal and
specified output skews and full-swing logic levels (LVTTL).
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.42 to 1.6 ns are deter-
mined by the operating frequency with outputs able to skew up
to ±6 time units from their nominal “zero” skew position. The
completely integrated PLL allows external load and trans-
mission line delay effects to be canceled. When this “zero
delay” capability of the LVPSCB is combined with the
selectable output skew functions, the user can create
output-to-output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility
minimizes clock distribution difficulty while allowing maximum
system clock speed and flexibility.
Pin Configuration
3F1
4F0
4F1
VCCQ
VCCN4
4Q1
4Q0
GND
GND
4 3 2 1 32 31 30
5 29
6 28
7 27
8 26
9 CY7C9915
10
25
24
11 23
12 22
13 21
14 15 16 17 18 19 20
2F0
GND
1F1
1F0
VCCN1
1Q0
1Q1
GND
GND
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07687 Rev. *A
Revised April 29, 2005
1 page  
PRELIMINARY
CY7C9915
proper selection of the xFn inputs. For example a +10 tU
between REF and 3Qx can be achieved by connecting 1Q0 to
FB and setting 1F0 = 1F1 = GND, 3F0 = MID, and 3F1 = High.
(Since FB aligns at –4 tU and 3Qx skews to +6 tU, a total of
+10 tU skew is realized.) Many other configurations can be
realized by skewing both the output used as the FB input and
skewing the other outputs.
REF
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
www.DataSheet4U.c2oFm1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
Figure 4. Inverted Output Connections
Figure 4 shows an example of the invert function of the
LVPSCB. In this example the 4Q0 output used as the FB input
is programmed for invert (4F0 = 4F1 = HIGH) while the other
three pairs of outputs are programmed for zero skew. When
4F0 and 4F1 are tied HIGH, 4Q0 and 4Q1 become inverted
zero phase outputs. The PLL aligns the rising edge of the FB
input with the rising edge of the REF. This causes the 1Q, 2Q,
and 3Q outputs to become the “inverted” outputs with respect
to the REF input. By selecting which output is connect to FB,
it is possible to have 2 inverted and 6 non-inverted outputs or
6 inverted and 2 non-inverted outputs. The correct configu-
ration would be determined by the need for more (or fewer)
inverted outputs. 1Q, 2Q, and 3Q outputs can also be skewed
to compensate for varying trace delays independent of
inversion on 4Q.
REF
20 MHz
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
40 MHz
20 MHz
80 MHz
Figure 5. Frequency Multiplier with Skew Connections
Figure 5 illustrates the LVPSCB configured as a clock multi-
plier. The 3Q0 output is programmed to divide by four and is
fed back to FB. This causes the PLL to increase its frequency
until the 3Q0 and 3Q1 outputs are locked at 20 MHz while the
1Qx and 2Qx outputs run at 80 MHz. The 4Q0 and 4Q1
outputs are programmed to divide by two, which results in a
40-MHz waveform at these outputs. Note that the 20- and
40-MHz clocks fall simultaneously and are out of phase on
their rising edge. This will allow the designer to use the rising
edges of the 1⁄2 frequency and 1⁄4 frequency outputs without
concern for rising-edge skew. The 2Q0, 2Q1, 1Q0, and 1Q1
outputs run at 80 MHz and are skewed by programming their
select inputs accordingly. Note that the FS pin is wired for
80-MHz operation because that is the frequency of the fastest
output.
REF
20 MHz
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
10 MHz
5 MHz
20 MHz
Figure 6. Frequency Divider Connections
Figure 6 demonstrates the LVPSCB in a clock divider appli-
cation. 2Q0 is fed back to the FB input and programmed for
zero skew. 3Qx is programmed to divide by four. 4Qx is
programmed to divide by two. Note that the falling edges of the
4Qx and 3Qx outputs are aligned. This allows use of the rising
edges of the 1⁄2 frequency and 1⁄4 frequency without concern
for skew mismatch. The 1Qx outputs are programmed to zero
skew and are aligned with the 2Qx outputs. In this example,
the FS input is grounded to configure the device in the 15- to
30-MHz range since the highest frequency output is running at
20 MHz.
Figure 7 shows some of the functions that are selectable on
the 3Qx and 4Qx outputs. These include inverted outputs and
outputs that offer divide-by-2 and divide-by-4 timing. An
inverted output allows the system designer to clock different
subsystems on opposite edges, without suffering from the
pulse asymmetry typical of non-ideal loading. This function
allows the two subsystems to each be clocked 180 degrees
out of phase, but still to be aligned within the skew spec.
The divided outputs offer a zero-delay divider for portions of
the system that need the clock to be divided by either two or
four, and still remain within a narrow skew of the “1X” clock.
Without this feature, an external divider would need to be
added, and the propagation delay of the divider would add to
the skew between the different clock signals.
These divided outputs, coupled with the Phase Locked Loop,
allow the LVPSCB to multiply the clock rate at the REF input
by either two or four. This mode will enable the designer to
distribute a low-frequency clock between various portions of
the system, and then locally multiply the clock rate to a more
suitable frequency, while still maintaining the low-skew charac-
teristics of the clock driver. The LVPSCB can perform all of the
functions described above at the same time. It can multiply by
Document #: 38-07687 Rev. *A
Page 5 of 14
5 Page 
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)[2, 13]
Parameter
Description
FBW
Loop Bandwidth
tU
tSKEWPR
tSKEW0
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tDEV
Programmable Skew Unit
Zero Output Matched-Pair Skew (XQ0, XQ1)[14, 16]
Zero Output Skew (All Outputs)[14, 17,18]
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)[14, 19]
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)[14, 19]
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)[14, 19]
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)[14, 19]
Device-to-Device Skew[15, 20]
tPD Propagation Delay, REF Rise to FB Rise
tODC
Output Duty Cycle[21]
www.DataShtOeReIStE4U.com Output Rise Time[22, 22]
tOFALL
Output Fall Time[22, 22]
tLOCK
PLL Lock Time[23]
tJR
Cycle-to-Cycle Output Jitter
RMS, fNOM > 22MHz[15]
RMS, fNOM < 22MHz[15]
Peak, fNOM > 22MHz[15]
Peak, fNOM < 22MHz[15]
tPJ Period Jitter
RMS, fNOM > 22MHz[15]
RMS, fNOM < 22MHz[15]
Peak-to-Peak,
22MHz[15]
fNOM
>
Peak-to-Peak,
22MHz[15]
fNOM
<
Min.
–
–
–
–
–
–
–
–
–0.5
45
0.15
0.15
–
–
–
–
–
–
–
–
–
CY7C9915
CY7C9915-5
Typ. Max.
1–
See Table 1
0.05 0.25
0.1 0.5
0.1 0.7
0.3 1.0
0.25 0.7
0.25 1.0
– 1.25
– +0.5
50 55
0.5 1.2
0.5 1.2
– 0.5
– 15
– 30
– 100
– 200
– 25
– 50
– 150
– 300
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
%
ns
ns
ms
ps
ps
ps
ps
Document #: 38-07687 Rev. *A
Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CY7C9915.PDF ] | |
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