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PDF SII3114 Data sheet ( Hoja de datos )
| Número de pieza | SII3114 | |
| Descripción | SATALink PCI-X to 4-Port Host Controller | |
| Fabricantes | Silicon image | |
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Data Sheet
www.DataSheet4U.com
SiI3114
PCI to Serial ATA Controller
Data Sheet
Document # SiI-DS-0103-D
1 page  
Silicon Image, Inc.
SiI3114 PCI to Serial ATA Controller
Data Sheet
FIFO Port – Channel X.......................................................................................................................... 60
FIFO Pointers1– Channel X .................................................................................................................. 61
FIFO Pointers2– Channel X .................................................................................................................. 61
Channel X Task File Register 0 ............................................................................................................. 62
Channel X Task File Register 1 ............................................................................................................. 62
Channel X Task File Register 2 ............................................................................................................. 63
Channel X Read Ahead Data ................................................................................................................ 63
Channel X Task File Register 0 – Command Buffering......................................................................... 64
Channel X Task File Register 1 – Command Buffering......................................................................... 64
Channel X Extended Task File Register – Command Buffering ........................................................... 65
Channel X Virtual DMA/PIO Read Ahead Byte Count .......................................................................... 65
Channel X Task File Configuration + Status.......................................................................................... 65
Data Transfer Mode – Channel X.......................................................................................................... 66
Serial ATA SControl ............................................................................................................................... 67
Serial ATA SStatus................................................................................................................................. 68
Serial ATA SError................................................................................................................................... 69
Serial ATA SActive ................................................................................................................................. 70
www.DataSheeSSt4MeUriisa.ccl A.o..Tm..A...P..H...Y...C...o..n..f.i.g..u..r.a..t.i.o..n................................................................................................................................................................................................................................
70
71
SIEN ...................................................................................................................................................... 72
SFISCfg ................................................................................................................................................. 73
RxFIS0-RxFIS6 ..................................................................................................................................... 73
Programming Sequences .......................................................................................................................... 74
Recommended Initialization Sequence for the SiI3114...................................................................... 74
Serial ATA Device Initialization .............................................................................................................. 75
Issue ATA Command............................................................................................................................... 76
PIO Mode Read/Write Operation............................................................................................................ 76
Watchdog Timer Operation .................................................................................................................... 77
PIO Mode Read Ahead Operation.......................................................................................................... 78
MDMA/UDMA Read/Write Operation ..................................................................................................... 78
Virtual DMA Read/Write Operation........................................................................................................ 79
Using Virtual DMA with Non-DMA Capable Devices............................................................................. 79
Using Virtual DMA with DMA Capable Devices..................................................................................... 81
Second PCI Bus Master Registers Usage ............................................................................................ 82
Power Management.................................................................................................................................... 83
Power Management Summary............................................................................................................... 83
Partial Power Management Mode.......................................................................................................... 83
Slumber Power Management Mode ...................................................................................................... 83
Hot Plug Support .................................................................................................................................... 84
FIS Support ................................................................................................................................................. 85
FIS Summary ........................................................................................................................................... 85
FIS Transmission .................................................................................................................................... 86
FIS Reception .......................................................................................................................................... 86
FIS Types Not Affiliated with Current ATA/ATAPI Operations ............................................................ 89
BIST Support ......................................................................................................................................... 89
BIST Signals.......................................................................................................................................... 89
DMA Setup ............................................................................................................................................ 89
© 2007 Silicon Image, Inc.
v
SiI-DS-0103-D
5 Page 
Silicon Image, Inc.
SiI3114 PCI to Serial ATA Controller
Data Sheet
• Configuration Read
• Configuration Write
• Memory Read
• Memory Write
All other PCI cycles are ignored by the SiI3114.
As a PCI master, the SiI3114 generates the following PCI bus operations:
• Memory Read Multiple
• Memory Read
• Memory Write
PCI Configuration Space
This section describes how the SiI3114 implements the required PCI configuration register space. The intent of
PCI configuration space definition is to provide an appropriate set of configuration registers that satisfy the needs
of current and anticipated system configuration mechanisms, without specifying those mechanisms or otherwise
placing constraints on their use. These registers allow for:
www.DataShee•t4FUu.lcl doemvice relocation (including interrupt binding)
• Installation, configurations, and booting without user interventions
• System address map construction by device-independent software
Figure 1 illustrates the address line assignments during the configuration cycle.
Bit
Number 31
11 10
87
21
Bit
0 Number
Don’t Care
3-Bit
Function
Number
6-Bit
Register
Number
Figure 1. Address Lines During Configuration Cycle
2-Bit
Type
Number
The SiI3114 only responds to Type 0 configuration cycles. Type 1 cycles, which pass a configuration request on
to another PCI bus, are ignored.
The address phase during a SiI3114 configuration cycle indicates the function number and register number being
addressed which can be decoded by observing the status of the address lines AD[31:0].
The value of the signal lines AD[7:2] during the address phase of configuration cycles selects the register of the
configuration space to access. Valid values are between 0 and 15, inclusive. Accessing registers outside this
range results in an all-0s value being returned on reads, and no action being taken on writes.
The Class Code register contains the Class Code, Sub-Class Code, and Register-Level Programming Interface
registers.
All writable bits in the configuration space except offset 44h, 8Ch are reset to their defaults by the hardware reset,
PCI RESET (RST#) asserted. After reset, the SiI3114 is disabled and will only respond to PCI configuration write
and PCI configuration read cycles.
Deviations from the Specification
The SiI3114 product has been developed and tested to the specification listed in this document. As a result of
testing and customer feedback, we may become aware of deviations to the specification that could affect the
component's operation. To ensure awareness of these deviations by anyone considering the use of the SiI3114,
we have included an Errata section at the end of this specification. Please ensure that the Errata section is
© 2007 Silicon Image, Inc.
3
SiI-DS-0103-D
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