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PDF CY7C954DX Data sheet ( Hoja de datos )
| Número de pieza | CY7C954DX | |
| Descripción | Atm Hotlink Transceiver | |
| Fabricantes | Cypress Semiconductor | |
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54DX
CY7C954DX
Features
• Second-generation HOTLink® technology
• UTOPIA level I and II compatible host bus interface
• Three-bit Multi-PHY address capability built-in
• Three user-selectable Start Of Cell marker/indicators
• Embedded 256-character synchronous FIFOs
• Built-in ATM Header Error Control (HEC)
• Automatic Transmit-HEC insertion & Receiver-HEC
www.DataSheet4Uc.choemck
• FIFO cell-level flushing of invalid ATM cells
• ATM Forum, Fibre Channel, and ESCON® compliant
8B/10B encoder/decoder
• 50- to 200-MBaud serial signaling rate
• Internal PLLs with no external PLL components
• Dual differential PECL-compatible serial inputs
• Dual differential PECL-compatible serial outputs
• Compatible with fiber-optic modules and copper cables
• Built-In Self-Test (BIST) for link testing
• Link Quality Indicator
• Single +5.0V ±10% supply
• 100-pin TQFP
• 0.35µ CMOS technology
Functional Description
The 200-MBaud CY7C954DX HOTLink Transceiver is a point-
to-point communications building block allowing the transfer of
data over high-speed serial links (optical fiber, balanced, and
unbalanced copper transmission lines) at speeds ranging be-
tween 50 and 200 MBaud. The transmit section accepts par-
allel data of selectable width and converts it to serial data,
while the receiver section accepts serial data and converts it
to parallel data of selectable width. Figure 1 illustrates typical
connections between two independent host systems and cor-
responding CY7C954DX parts. As a second-generation
HOTLink device, the CY7C954DX provides enhanced levels of
ATM HOTLink® Transceiver
technology, functionality, and integration over the field proven
CY7B923/933 HOTLink.
The transmit section of the CY7C954DX HOTLink has been
configured to accept 8-bit data characters on each clock cycle,
and store the parallel data into an internal Transmit FIFO. Data
is read from the Transmit FIFO and is encoded using an em-
bedded 8B/10B encoder to improve its serial transmission
characteristics. These encoded characters are then serialized
and output from two Pseudo ECL (ECL referenced to +5.0V)
compatible differential transmission line drivers at a bit-rate of
10 times the input reference clock.
The receive section of the CY7C954DX HOTLink accepts a
serial bit-stream from one of two PECL-compatible differential
line receivers and, using a completely integrated PLL Clock
Synchronizer, recovers the timing information necessary for
data reconstruction. The recovered bit stream is deserialized
and framed into characters, 8B/10B decoded, and checked for
transmission errors. Recovered decoded characters are re-
constructed into 8-bit data characters, written to an internal
Receive FIFO, and presented to the destination host system.
For those systems requiring even greater FIFO storage capa-
bility, external FIFOs may be directly coupled to the
CY7C954DX device through the parallel interface without ad-
ditional glue-logic for single PHY connections.
The TTL parallel I/O interface may be configured as either a
FIFO (configurable for UTOPIA emulation or for depth expan-
sion through external FIFOs) or as a pipeline register extender.
The FIFO configurations are optimized for transport of time-
independent (asynchronous) 8-bit character-oriented data
across a link. A Built-In Self-Test (BIST) pattern generator and
checker allows for at-speed testing of the high-speed serial
data paths in both the transmit and receive sections, and
across the interconnecting links.
HOTLink devices are ideal for a variety of applications where
parallel interfaces can be replaced with high-speed, point-to-
point serial links. Some applications include interconnecting
workstations, backplanes, servers, mass storage, and video
transmission equipment.
Data
Receive
Control
Status
Data
Transmit
CY7C954DX
Serial Link
Serial Link
CY7C954DX
Transmit
Data
Control
Status
Receive
Data
Figure 1. HOTLink System Connections
HOTLink is a registered trademark of Cypress Semiconductor Corporation.
ESCON is a registered trademark of International Business Machines.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-02007 Rev. **
Revised June 10, 2000
1 page  
CY7C954DX
Pin Descriptions (continued)
Pin #
Name
16 TXRST*
7 TXBISTEN*
Receive Path Signals
www.DataSheet4U.com
41, 43, RXDATA[7:0]
45, 47,
48, 53,
59, 61
29 RXRVS
23 RXSOC
65 RXSC/D*
69 RXEN*
71,31, RXADDR[2:0]
33
8 RXCLK
I/O Characteristics
Signal Description
TTL input, internal
pull-up, sampled on
TXCLK↑,
Internal Pull-Up
Transmit FIFO Reset.
When TXRST* is sampled asserted (LOW) for eight or more TXCLK cycles, a
reset operation is started on the Transmit FIFO.
TTL input,
asynchronous,
Internal Pull-Up
Transmitter BIST Enable.
When TXBISTEN* is LOW, the transmitter generates a 511-character repeat-
ing sequence, that can be used to validate link integrity. The transmitter returns
to normal operation when TXBISTEN* is HIGH. All Transmit FIFO read oper-
ations are suspended when BIST is active.
3-state TTL output,
changes following
RXCLK↑
3-state TTL output,
changes following
RXCLK↑,
Internal Pull-Up
3-state TTL output,
changes following
RXCLK↑
3-state TTL output,
changes following
RXCLK↑
TTL input, sampled
on RXCLK↑,
Internal Pull-Up
TTL input, sampled
on RXCLK↑
TTL output clock,
Internal Pull-Up
Parallel Data Output.
These outputs change following the rising edge of RXCLK, when enabled to
output data (the device RXADDR[2:0] address matches ADDRSEL[2:0] and
selected by RXEN*).
Received Violation Symbol Indicator.
In Receive mode (11), this output is the indicator that data has been received
continuing errors, and is decoded in conjunction with RXSC/D* and RXSOC,
per Table 4, to indicate the presence of specific Special Character codes in the
received data stream.
This output is unused for the other receive modes, except that RXRVS is used
to report character mismatches when RXBISTEN* is LOW
This output changes following the rising edge of RXCLK, when enabled to
output data (the device RXADDR[2:0] address matches ADDRSEL[2:0] and
selected by RXEN*).
Receive Start Of Cell.
This output is one of the indicators for the start of a cell and is decoded in
conjunction with RXSC/D* and RXRVS, per Table 4, to indicate the presence
of specific Special Character codes in the received data stream.
This output changes following the rising edge of RXCLK, when enabled to
output data (the device RXADDR[2:0] address matches ADDRSEL[2:0] and
selected by RXEN*).
Received Special Character or Data Indicator.
This signal is use to differentiate between Special Characters and Data bytes.
It is also decoded in conjunction with RXSOC and RXRVS, per Table 4, to
indicate the presence of specific Special Character codes in the received data
stream.
This output changes following the rising edge of RXCLK, when enabled to
output data (the device RXADDR[2:0] address matches ADDRSEL[2:0] and
selected by RXEN*).
Receive Enable.
Data enable for the RXDATA bus write and read operations. Active LOW when
configured for UTOPIA timing, active HIGH when configured for Cascade tim-
ing as determined by the EXTFIFO pin.
Receive Address Input.
This is the three-bit Receive Port address that is matched to ADDRSEL[2:0] to
enable data transfer to the receiving system.
Receive Clock.
This clock is the Receive interface input clock and is used to control Receive
FIFO read, reset, and serial register access operations.
Document #: 38-02007 Rev. **
Page 5 of 43
5 Page 
CY7C954DX
When the TXSOC bit (as read from the Transmit FIFO) is
HIGH, an extra character is inserted into the data stream. This
extra character is always a Special Character code (see Table
9) that is used to inform the remote receiver that the immedi-
ately following character should be interpreted differently from
its normal meaning. The associated character present on
TXDATA[x:0] is always encoded as a data character.
The 100b (TXSOC = 1, TXSC/D* = 0, and TXSVS = 0), 110b
and 111b combinations are used as markers for the start of a
cell, frame, or packet of data being sent across the interface.
When a character is read from the Transmit FIFO with these
bits set, a C8.0, C9.0, or C10.0 Special Character code is sent
to the encoder prior to sending the associated data character.
www.DataSheeTt4hUe.c1o0m1b encoding has the same function as the 001b and
011b normal data modes. It instructs the encoder to discard
the associated data character and to replace it with a C0.7
Exception character.
The 110b encoding might be used for a context-based Start of
Cell marker (SOC with one of three modifiers), or it could be
used to expand the command space beyond that available with
the default 8B/10B code (SC/D* with a modifier). The 8B/10B
code normally supports a data space of 256 data characters,
and a command (non-data) space of twelve command charac-
ters (C0.0-C11.0 in Table 9). For those data links where these
few commands are not sufficient, the 110b encoding can be
used to mark the associated data as an extended command.
This expands the command space to 256 commands (in addi-
tion to some of the present twelve). When a character is read
from the Transmit FIFO with these bits set, a C9.0 Special
Character code is sent to the encoder prior to sending the data
character.
Note: Since this character is interpreted as a “Start of Cell”
marker, care should be taken in its placement. If the receiver
is in Receive Mode (00, 01,10) placements that create “illegal
ATM cells” will be discarded.
The 111b encoding might be used for a different context-based
Start of Cell marker (SOC with one of three modifiers).
When a character is read from the Transmit FIFO with these
bits set, a C10.0 Special Character is sent to the encoder prior
to sending the associated data character.
Header Error Check Generation and insertion
If HEC generation is enabled (although not really a “Receive
Mode”, this function is enabled by 00b on the RXMODE[1:0]
pins; see Table 5) the transmitter will overwrite the 5th byte of
each ATM cell with the appropriate internally generated HEC
code. This code is a CRC of the first four bytes in the ATM
header (the first four bytes after the Transmit Start of Cell
Marker) as is defined by the ATM Forum spec I413.
Encoder Block
The Encoder logic block performs two primary functions: en-
coding the data for serial transmission and generating BIST
(Built-In Self Test) patterns to allow at-speed link and device
testing.
BIST LFSR
The Encoder logic block operates on data stored in a register.
This register accepts information directly from the Transmit
FIFO, the Transmit Input Register, the 10/8 Byte-Packer, or
from the Transmit Control State Machine when it inserts spe-
cial characters into the data stream.
This same register is converted into a Linear-Feedback Shift-
Register (LFSR) when the Built-In Self-Test (BIST) pattern
generator is enabled (TXBISTEN* is LOW). When enabled,
this LFSR generates a 511-character sequence that includes
all Data and Special Character codes, including the explicit
violation symbols. This provides a predictable but pseudo-
random sequence that can be matched to an identical LFSR
in the Receiver.
The specific patterns generated are described in detail in the
Cypress application note “HOTLink Built-In Self-Test.” The se-
quence generated by the CY7C954DX is identical to that in the
CY7B923, CY7C924, and CY7B929, allowing interoperable
systems to be built when used at compatible serial signaling
rates and appropriate ATM Cell handling logic, since none of
these are ATM aware.
Encoder
The data passed through the Transmit FIFO and formatter, or
as received directly from the Transmit Input Register, is seldom
in a form suitable for transmission across a serial link. The
characters must usually be processed or transformed to guar-
antee:
• a minimum transition density (to allow the serial receiver
PLL to extract a clock from the data stream),
• a DC-balance in the signaling (to prevent baseline wander),
• run-length limits in the serial data (to limit the bandwidth of
the link), and
• some way to allow the remote receiver to determine the
correct character boundaries (framing).
The CY7C954DX contains an integrated 8B/10B encoder that
accepts 8-bit data characters and converts these into 10-bit
transmission characters that have been optimized for transport
on serial communications links. The operation of the 8B/10B
encoding algorithm is described in detail later in this
datasheet, and the complete encoding tables are listed in Ta-
bles 8 and 9.
The transmit data characters (as passed through the Transmit
FIFO and formatter) are converted to either a 10-bit Data symbol or
a 10-bit Special Character, depending upon the state of the
TXSC/D* input. If TXSC/D* is HIGH, the data inputs represent a
Special Character code and are encoded using the Special Char-
acter encoding rules in Table 9. If TXSC/D* is LOW, the data inputs
are encoded using the Data Character encoding in Table 8.
If this bit (TXSVS) is HIGH, the respective character is re-
placed with an SVS (C0.7) character. This can be used to
check error handling system-logic in the receiver controller or for
proprietary applications. This will cause the entire ATM cell to be
discarded, except in Receive Mode (11), which will pass the error
character to down stream logic.
The 8B/10B encoder is standards compliant with ANSI/NCITS
ASC X3.230-1994 (Fibre Channel), IEEE 802.3z (Gigabit
Ethernet), the IBM ESCON and FICON channels, and ATM
Forum standards for data transport.
Transmit Shifter
The Transmit Shifter accepts 10-bit parallel data from the En-
coder block once each character time, and shifts it out the
serial interface output buffers using a PLL-multiplied bit-clock.
This bit-clock runs at 2.5, 5, or 10 times the REFCLK rate as
Document #: 38-02007 Rev. **
Page 11 of 43
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