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PDF MX26L6419 Data sheet ( Hoja de datos )
| Número de pieza | MX26L6419 | |
| Descripción | 64M [x16] SINGLE 3V PAGE MODE MTP MEMORY | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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FEATURES
ADVANCED INFORMATION
MX26L6419
64M[x16] SINGLE3VPAGEMODEMTPMEMORY
• 3.0V to 3.6V operation voltage
• Block Structure
- 64 x 64Kword Erase Blocks
• Fast random / page mode access time
- 100/25 ns Read Access Time (page depth:8-word)
• 128-bit Protection Register
- 64-bit Unique Device Identifier
www.DataSheet4U-.c6o4m-bit User Programmable OTP Cells
• 16-Word Write Buffer
- 14 us/word Effective Programming Time
• Enhanced Data Protection Features Absolute Protec-
tion with VPEN = GND
- Flexible Block Locking
- Block Erase/Program Lockout during Power Transi-
tions
Performance
• Low power dissipation
- typical 15mA active current for page mode read
- 80uA/(max.) standby current
• High Performance
- Block erase time: 2s typ.
- Word programming time: 210us typ.
- Block programming time: 0.8s typ. (using Write to
Buffer Command)
• Program/Erase Endurance cycles: 100 cycles
Software Feature
• Support Common Flash Interface (CFI)
- MTP device parameters stored on the device and
provide the host system to access.
Hardware Feature
• ACC pin
- 12V VPP for fast program/erase mode.
• VPEN pin
- For Erase /Program/ Block Lock enable.
• VCCQ Pin
- The output buffer power supply, control the device 's
output voltage.
• RESET pin
- Hardware reset
Packaging
- 48-Lead TSOP
Technology
- Two bits per cell Nbit (0.25u) MTP Technology
GENERAL DESCRIPTION
The MXIC's MX26L6419 series MTP use the most ad-
vance 2 bits/cell Nbit technology, double the storage ca-
pacity of memory cell. The device provide the high den-
sity MTP memory solution with reliable performance and
most cost-effective.
The device organized as by 16 bits of output bus. The
device is packaged in 48-Lead TSOP. It is designed to
be reprogrammed and erased in system or in standard
EPROM programmers.
The device offers fast access time and allowing opera-
tion of high-speed microprocessors without wait states.
The device augment EPROM functionality with in-circuit
electrical erasure and programming. The device uses a
command register to manage this functionality.
The MXIC's Nbit technology reliably stores memory con-
tents even after the specific erase and program cycles.
The MXIC cell is designed to optimize the erase and
program mechanisms by utilizing the dielectric's charac-
ter to trap or release charges from ONO layer.
The device uses a 3.0V to 3.6V VCC supply to perform
the High Reliability Erase and auto Program/Erase algo-
rithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
P/N:PM0946
REV. 0.3, OCT. 08, 2003
1
1 page  
MX26L6419
Table 1. Bus Operations
Command
Sequence
www.DataSheet4UN.ocotems
Read
Array
Output
Disable
Standby RESET Read ID
Mode/
Power
Down
Mode
Read
Query
Read
Read
Status Status
(WSM off) (WSM on)
Write
3,4 8,9
RESET
VIH VIH VIH
VIL VIH
VIH VIH
VIH
VIH
CE
Enabled Enabled Disabled X
Enabled Enabled Enabled Enabled
Enabled
OE (1)
VIL VIH X
X VIL VIL VIL
VIL
VIH
WE (1)
VIH VIH X
X VIH VIH VIH
VIH
VIL
Address
VPEN
XXX
XXX
X See See X
Figure 2 Table 5
XX
XX
X
X
X
VPENH
Q (2)
Data out High Z High Z
High Z Note 6
Note 7
Data out
Q7=Data out Data in
Q15-8=High Z
Q6-0=High Z
NOTES:
1. OE and WE should never be enabled simultaneously.
2. Q refers to Q0~Q15.
3. Refer to DC Characteristics. When VPEN < VPENLK , memory contents can be read, but not altered.
4. X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN . See DC Characteristics for
VPENLK and VPENH voltages.
5. High Z will be VOH with an external pull-up resistor.
6. See Section , "Read Identifier Codes" for read identifier code data.
7. See Section , "Read Query Mode Command" for read query data.
8. Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPEN=
VPENH and VCC is within specification.
9. Refer to Table 2 on page 7 for valid DIN during a write operation.
P/N:PM0946
REV. 0.3, OCT. 08, 2003
5
5 Page 
MX26L6419
In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been
dropped. In addition, since the upper byte of word-wide devices is always "00h",” the leading "00" has been dropped
from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h
on the upper byte in this mode.
Table 3. Summary of Query Structure Output as a Function of Device and Mode
Device
Type/Mode
www.DataSheet4U.com
x16 device
x16 mode
x16 device
x8 mode
Query start location in
maximum device bus
width addresses
10h
N/A (1)
Query data with maximum
device bus width addressing
Hex
Offset
10:
11:
12:
Hex
Code
0051
0052
0059
ASCII
Value
"Q"
"R"
"Y"
N/A (1)
Query data with byte
addressing
Hex
Offset
20:
21:
22:
20:
21:
22:
Hex
Code
51
00
52
51
51
52
ASCII
Value
"Q"
"Null"
"R"
"Q"
"Q"
"R"
NOTE:
1. The system must drive the lowest order addresses to access all the device's array data when the device is
configured in x8 mode.Therefore, word addressing, where these lower addresses are not toggled by the system, is
"Not Applicable" for x8-configured devices.
Table 4. Example of Query Structure Output of a x16- and x8-Capable Device
Offset
A15-A0
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
...
Word Addressing
Hex Code
Value
D15 - D0
0051
"Q"
0052
"R"
0059
"Y"
P_IDLO
P_ID
HI
PLO
PrVendor
ID#
PrVendor
PHI TblAdr
A_IDLO
A_ID
HI
...
AltVendor
ID#
...
Offset
A7-A0
20h
21h
22h
23h
24h
25h
26h
27h
28h
...
Byte Addressing
Hex Code
Value
D7 - D0
51 "Q"
51 "Q"
52 "R"
52 "R"
59 "Y"
59 "Y"
P_IDLO
P_IDLO
P_ID
HI
...
PrVendor
ID#
ID#
...
P/N:PM0946
REV. 0.3, OCT. 08, 2003
11
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