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PDF SST31LF021E Data sheet ( Hoja de datos )
| Número de pieza | SST31LF021E | |
| Descripción | 2 Mbit Flash 1 Mbit SRAM ComboMemory | |
| Fabricantes | SST | |
| Logotipo |  |
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2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
SST31LF021 / 021E2 Mb Flash (x8) + 1 Mb SRAM (x8) Monolithic ComboMemories
FEATURES:
Data Sheet
• Monolithic Flash + SRAM ComboMemory
– SST31LF021/021E: 256K x8 Flash + 128K x8 SRAM
• Single 3.0-3.6V Read and Write Operations
• Concurrent Operation
– Read from or Write to SRAM while
Erase/Program Flash
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
www.DataSheet4U–.comGreater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 10 mA (typical) for Flash and
20 mA (typical) for SRAM Read
– Standby Current: 10 µA (typical)
• Flash Sector-Erase Capability
– Uniform 4 KByte sectors
• Latched Address and Data for Flash
• Fast Read Access Times:
– SST31LF021
– SST31LF021E
Flash: 70 ns
SRAM: 70 ns
Flash: 300 ns
SRAM: 300 ns
• Flash Fast Erase and Byte-Program:
– Sector-Erase Time: 18 ms (typical)
– Bank-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Bank Rewrite Time: 4 seconds (typical)
• Flash Automatic Erase and Program Timing
– Internal VPP Generation
• Flash End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Package Available
– 32-lead TSOP (8mm x 14mm)
PRODUCT DESCRIPTION
The SST31LF021/021E devices are a 256K x8 CMOS
flash memory bank combined with a 128K x8 or 32K x8
CMOS SRAM memory bank manufactured with SST’s
proprietary, high performance SuperFlash technology. Two
pinout standards are available for these devices. The
SST31LF021 conform to JEDEC standard flash pinouts
and the SST31LF021E conforms to standard EPROM
pinouts. The SST31LF021/021E devices write (SRAM or
flash) with a 3.0-3.6V power supply. The monolithic
SST31LF021/021E devices conform to Software Data
Protect (SDP) commands for x8 EEPROMs.
Featuring high performance Byte-Program, the flash
memory bank provides a maximum Byte-Program time of
20 µsec. The entire flash memory bank can be erased and
programmed byte-by-byte in typically 4 seconds, when
using interface features such as Toggle Bit or Data# Poll-
ing to indicate the completion of Program operation. To
protect against inadvertent flash write, the SST31LF021/
021E devices have on-chip hardware and Software Data
Protection schemes. Designed, manufactured, and tested
for a wide spectrum of applications, the SST31LF021/
021E devices are offered with a guaranteed endurance of
10,000 cycles. Data retention is rated at greater than 100
years.
The SST31LF021/021E operate as two independent mem-
ory banks with respective bank enable signals. The SRAM
and flash memory banks are superimposed in the same
memory address space. Both memory banks share com-
mon address lines, data lines, WE# and OE#. The memory
bank selection is done by memory bank enable signals.
The SRAM bank enable signal, BES# selects the SRAM
bank and the flash memory bank enable signal, BEF#
selects the flash memory bank. The WE# signal has to be
used with Software Data Protection (SDP) command
sequence when controlling the Erase and Program opera-
tions in the flash memory bank. The SDP command
sequence protects the data stored in the flash memory
bank from accidental alteration.
The SST31LF021/021E provide the added functionality of
being able to simultaneously read from or write to the
SRAM bank while erasing or programming in the flash
memory bank. The SRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Byte-Program concurrently. All flash
memory Erase and Program operations will automatically
latch the input address and data signals and complete the
operation in background without further input stimulus
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01
392
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
1 page  
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
internal Program or Erase operation. See Table 4 for soft-
ware command codes, Figure 12 for timing waveform and
Figure 18 for a flowchart.
Design Considerations
SST recommends a high frequency 0.1 µF ceramic capac-
itor to be placed as close as possible between VDD and
VSS, e.g., less than 1 cm away from the VDD pin of the
device. Additionally, a low frequency 4.7 µF electrolytic
capacitor from VDD to VSS should be placed within 1 cm of
the VDD pin.
FUNCTIONAL BLOCK DIAGRAM
www.DataSheet4U.com
Address Buffers
SRAM
AMS - A0
BES#
BEF#
OE#
WE#
Control Logic
Address Buffers
& Latches
Note: AMS = Most Significant Address
SuperFlash
Memory
I/O Buffers
DQ7 - DQ0
392 ILL B1.2
SST31LF021E
A11
A9
A8
A13
A14
A17
BES#
VDD
WE#
A16
A15
A12
A7
A6
A5
A4
SST31LF021
A11
A9
A8
A13
A14
A17
WE#
VDD
BES#
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard Pinout
Top View
Die Up
SST31LF021
32 OE#
31 A10
30 BEF#
29 DQ7
28 DQ6
27 DQ5
26 DQ4
25 DQ3
24 VSS
23 DQ2
22 DQ1
21 DQ0
20 A0
19 A1
18 A2
17 A3
392 ILL F01.3
SST31LF021E
OE#
A10
BEF#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM)
©2001 Silicon Storage Technology, Inc.
5
S71137-03-000 10/01 392
5 Page 
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
ADDRESS A16-0
BEF#
www.DataSheet4U.com
BES#
OE#
WE#
DQ7-0
VIH
HIGH-Z
TRCS
TAAS
TBES
TOES
TOLZS
TBLZS
TOHS
DATA VALID
FIGURE 2: SRAM READ CYCLE TIMING DIAGRAM
TOHZS
TBHZS
DATA VALID
HIGH-Z
392 ILL F02.0
ADDRESS A16-0
OE#
BEF#
BES#
WE#
DQ7-0
TASTS
TWCS
ADDRESS
TAWS
TBWS
TWPS
TDSS
DATA VALID
FIGURE 3: SRAM WRITE CYCLE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
11
TWRS
TDHS
392 ILL F03.0
S71137-03-000 10/01 392
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet SST31LF021E.PDF ] | |
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