PDF CY9C6264 Data sheet ( Hoja de datos )

Número de pieza	CY9C6264
Descripción	8K X 8 Magnetic Nonvolatile CMOS RAM
Fabricantes	Cypress Semiconductor
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PRELIMINARY CY9C6264 8K x 8 Magnetic Nonvolatile CMOS RAM Features • 100% form-, fit-, and function-compatible with 8K × 8 micropower SRAM CY9C6264 — Fast Read and Write access: 70 ns — Voltage range: 4.5V–5.5V operation — Low active power: 495 mW (max.) www.DataSheet4U—.coLmow standby power, CMOS: 825 µW (max.) — Data retention current: 0 µA at VCC = 0V — Memory expansion with CE1, CE2, and OE features — TTL-compatible inputs and outputs — Automatic power-down when deselected • Replaces 8K × 8 battery backed (BB) SRAM, EEPROM, FeRAM, or Flash memory — Data is automatically protected during power loss — Write cycle endurance: >1015 Cycles — Data Retention: >10 Years — Shielded from external magnetic fields — Extra 16-bytes for device identification and tracking • Optional industrial temperature range: –40°C to +85°C • JEDEC STD 28-pin DIP (600-mil), 28-pin (300-mil) SOIC and TSOP packages Logic Block Diagram A9 A8 A7 A6 A5 A4 A3 A2 A1 CE 2 CE 1 WE OE INPUTBUFFER Silicon Sig. 512 × 128 ARRAY COLUMN DECODER POWER DOWN & WRITE PROTECT Description The CY9C6264 is a high-performance CMOS nonvolatile RAM employing an advanced magnetic RAM (MRAM) process. An MRAM is nonvolatile memory that operates as a RAM. It provides data retention for more than 10 years while eliminating the reliability concerns, functional disadvantages and system design complexities of battery-backed SRAM, EEPROM, Flash and FeRAM. Its fast writes and high write cycle endurance makes it superior to other types of nonvolatile memory. The CY9C6264 operates very similar to other SRAM devices. Memory read and write cycles require equal times. The MRAM memory is nonvolatile due to its unique magnetic process. Unlike BBSRAM, the CY9C6264 is truly a monolithic nonvol- atile memory. It provides the same functional benefits of a fast write without the serious disadvantages associated with modules and batteries or hybrid memory solutions. These capabilities make the CY9C6264 ideal for nonvolatile memory applications requiring frequent or rapid writes in a byte wide environment. The CY9C6264 is offered in both commercial and industrial temperature ranges. I/O0 I/O1 I/O2 I/O3 OE I/O4 A1 A2 I/O5 A3 CE2 I/O6 WE VCC NC I/O7 A4 A5 A6 A7 A8 A9 Pin Configurations SOIC/DIP Top View NC A4 A5 A6 A7 A8 A9 A10 A11 A12 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 VCC 27 WE 26 CE 2 25 A3 24 A2 23 A1 22 OE 21 A0 20 CE1 19 18 I/O7 I/O6 17 I/O5 16 I/O4 15 I/O3 22 21 A0 23 20 CE1 24 19 I/O7 25 18 I/O6 26 17 I/O5 27 TSOP I 16 I/O4 28 Top View 15 I/O3 1 (not to scale) 14 GND 2 13 I/O2 3 12 I/O1 4 11 I/O0 5 10 A12 6 9 A11 7 8 A10 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document # 38-15003 Rev. A Revised June 21, 2002 1 page PRELIMINARY CY9C6264 Switching Characteristics Over the Operating Range[5] CY9C6264-70 Parameter Description Min. Max. Unit Read Cycle tRC tAA tOHA tACE1 tACE2 www.DataSheet4tUDO.cEom tLZOE tHZOE tLZCE1 tLZCE2 tHZCE tPU tPD Write Cycle[8, 9] Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low-Z[6] OE HIGH to High-Z[6, 7] CE1 LOW to Low-Z[6] CE2 HIGH to Low-Z [6] CE1 CE2 HIGH to High-Z[6, LOW to High-Z [6, 7] 7] CE1 LOW to Power-up CE2 HIGH to Power-up CE1 HIGH to Power-down CE2 LOW to Power-down 70 70 5 70 70 35 5 25 5 5 25 0 70 ns ns ns ns ns ns ns ns ns ns ns ns ns tWC Write Cycle Time 70 ns tSCE1 CE1 LOW to Write End 60 ns tSCE2 CE2 HIGH to Write End 60 ns tAW Address Set-up to Write End 60 ns tHA Address Hold from Write End 0 ns tSA Address Set-up to Write Start 0 ns tPWE WE Pulse Width 50 ns tSD Data Set-up to Write End 30 ns tHD tHZWE tLZWE Data Hold from Write End WE LOW to High-Z[6, 7] WE HIGH to Low-Z[6] 0 ns 25 ns 5 ns Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE1 is less than tLZCE1, tHZCE2 is less than tLZCE2, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage. 8. The internal Write time of the memory is defined by the overlap of CE1 LOW or CE2 HIGH and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write. 9. The minimum write pulse width for Write cycle #3 (WE-controlled, OE LOW) is the sum of tHZWE and tSD. Document # 38-15003 Rev. A Page 5 of 11 5 Page PRELIMINARY Document Title: CY9C6264 8K x 8 Magnetic Nonvolatile CMOS RAM Document Number: 38-15003 REV. Orig. of ECN NO. Issue Date Change Description of Change ** 116317 06/11/02 NBP New Data Sheet A 116771 07/25/02 NBP Add state of memory bits at the time of shipment CY9C6264 www.DataSheet4U.com Document # 38-15003 Rev. A Page 11 of 11 11 Page

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